Video decoding system and memory interface apparatus

Abstract

A video decoding system and a memory interface thereof are disclosed, in which Y, Cb and Cr data of one macro block is rearranged to be simultaneously stored in an external memory and to be simultaneously read from the external memory, when storing video decoded data in the external memory, and outputting the stored data for motion compensation with a data bus of 96 bits, thereby decreasing an entire bandwidth of a video decoder and a local processing time.

What is claimed is:  
     
         1 . A video decoding system comprising: 
 a video decoder performing variable length decoding (VLD), inverse quantizing (IQ), inverse discrete cosine transform (IDCT) and motion compensation (MC) for a compressed bit stream, thereby restoring the bit stream to an original image signal;    an external memory simultaneously storing and outputting luminance (Y) signal and chrominance signals (Cb and Cr) of one macro block when storing the video decoded data with a data bus of 96 bits or outputting the stored data for a motion compensation; and    a memory interface rearranging Y, Cb and Cr data of the decoded macro block so as to be simultaneously stored in the external memory and to be simultaneously read from the external memory.    
     
     
         2 . The video decoding system of  claim 1 , wherein the memory interface composes one word with Y component of 8 pixels and Cb or Cr component of 4 pixels and controls to store and read 32 words by one external memory access.  
     
     
         3 . The video decoding system of  claim 2 , wherein the memory interface for writing the macro block in the external memory includes; 
 a first Y write buffer temporarily storing Y signal of 4 pixels in a horizontal direction of a specific low of a corresponding macro block and simultaneously outputting the Y signal,    a second Y write buffer temporarily storing Y signal of next 4 pixels in a horizontal direction of a specific low of a corresponding macro block and simultaneously outputting the Y signal,    a shuffler alternately rearranging input Cb and Cr chrominance signals and then outputting the rearranged Cb and Cr chrominance signals,    a CbCr write buffer temporarily storing the Cb and Cr chrominance signals being alternately output from the shuffler and simultaneously outputting the Cb or Cr chrominance signals, and    a memory arbiter de-multiplexing data of 32 bits being respectively output from the first and second Y write buffers and the CbCr write buffer and converting into data of 96 bits, and storing the data in a specific low/column address of the external memory.    
     
     
         4 . The video decoding system of  claim 3 , wherein the first and second write buffers and the CbCr write buffer are dual buffers, each buffer of 64×32 bits.  
     
     
         5 . The video decoding system of  claim 3 , wherein the memory interface further includes a video write controller controlling the first and second Y write buffers and the CbCr write buffer and generating and providing low/column address for writing data in the external memory to the memory arbiter.  
     
     
         6 . The video decoding system of  claim 2 , wherein the memory interface for reading macro blocks from the external memory includes; 
 a video read controller receiving field/frame prediction information for a motion compensation from the video decoder and generating a corresponding low/column address of the external memory,    a memory arbiter reading a macro block corresponding to the low/column address output from the video read controller and outputting the result,    a MUX dividing data of 96 bits output from the memory arbiter into data units of 32 bits,    a first Y read buffer temporarily storing Y signal of 32 bits corresponding to 4 pixels output from the MUX, and outputting the Y signal to the video decoder for the motion compensation,    a second Y read buffer temporarily storing Y signal of 32 bits corresponding to next 4 pixels output from the MUX, and outputting the Y signal to the video decoder for the motion compensation,    a de-shuffler restoring Cb and Cr signals of 32 bits corresponding to 4 pixels, being alternately output from the MUX, to an original order, and    a CbCr read buffer temporarily storing CbCr signal of 4 pixels being output from the de-shuffler, and outputting the CbCr signal to the video decoder for the motion compensation.    
     
     
         7 . The video decoding system of  claim 6 , wherein the video decoder performs half-pel interpolation of luminance (Y) signal output from the first and second read buffers and chrominance signals (CbCr) output from CbCr buffers in parallel.  
     
     
         8 . The video decoding system of  claim 6 , wherein the first and second read buffers and the CbCr read buffer are dual buffers, each buffer of 64×32.  
     
     
         9 . A memory interface apparatus of a video decoding system performing variable length decoding (VLD), inverse quantizing (IQ), inverse discrete cosine transform (IDCT) and motion compensation (MC) for a compressed bit stream with an external memory so as to restore the bit stream to an original image signal; wherein a memory interface is connected through a data bus of 96 bits between video decoding system and external memory, so that decoded luminance (Y) signal and chrominance signals (Cb and Cr) of one macro block are simultaneously stored in the external memory, and are rearranged so as to be simultaneously read.  
     
     
         10 . The memory interface apparatus of  claim 9 , wherein the memory interface composes one word with Y component of 8 pixels, and Cb or Cr component of 4 pixels, and controls to store and read 32 words by one external memory access.  
     
     
         11 . The memory interface apparatus of  claim 9 , wherein the memory interface includes; 
 a first Y write/read buffer receiving decoded video data or data stored in the external memory, temporarily storing Y signal of 4 pixels in a horizontal direction of a specific low to a corresponding macro block, and simultaneously outputting the Y signal,    a second Y write/read buffer receiving video decoded data or data stored in the external memory, temporarily storing Y signal of next 4 pixels in a horizontal direction of a specific low to a corresponding macro block, simultaneously, outputting the Y signal,    a shuffler alternately rearranging and outputting Cb and Cr chrominance signals when storing data in the external memory,    a de-shuffler arranging the Cb and Cr chrominance signals being read from the external memory in an original order and outputting the chrominance signals according to the original order when reading data from the external memory,    a CbCr write/read buffer temporarily storing Cb or Cr chrominance signals of 4 pixels in a horizontal direction of a specific low of a corresponding macro block from the shuffler or de-shuffler, and simultaneously outputting the Cb or Cr chrominance signals,    a memory arbiter de-multiplexing data of 32 bits being respectively output from the first and second Y write/read buffers and CbCr write/read buffer and converting into data of 96 bits, storing the result in a specific low/column address of the external memory, dividing the data of 96 bits read from the specific low/column address of the external memory into data unit of 32 bits, and outputting the result to the first and second Y writhe/read buffers and CbCr write/read buffer, and    a video write/read controller controlling write of the first and second Y write/read buffers and the CbCr write/read buffer, storing the data in the external memory, generating low/column address for reading the data from the external memory and then generating the low/column address to the memory arbiter.    
     
     
         12 . The memory interface apparatus of  claim 11 , wherein the first Y write/read buffer is a dual buffer, each buffer of 64×32.  
     
     
         13 . The memory interface apparatus of  claim 11 , wherein the second Y write/read buffer is a dual buffer, each buffer of 64×32.  
     
     
         14 . The memory interface apparatus of  claim 11 , wherein the CbCR write/read buffer is a dual buffer, each buffer of 64×32.