Magnetic random access memory

Abstract

A read block is formed from a plurality of TMR elements stacked in the vertical direction. One terminal of each TMR element in the read block is connected to a source line through a read select switch. The source line extends in the Y-direction and is connected to a ground point through a column select switch. The other terminal of each TMR element is independently connected to a corresponding one of read/write bit lines. Each read/write bit line extends in the Y-direction and is connected to a read circuit through the column select switch.

What is claimed is:  
     
         1 . A magnetic random access memory comprising: 
 memory cells which are stacked at stages to store data using a magnetoresistive effect;    a read select switch which commonly connect to one terminal of each of said memory cells; and    bit lines which arrange in correspondence with said memory cells and extend in a first direction,    wherein each of said memory cells has the other terminal independently connected to one of said bit lines, and said bit lines are electrically isolated each other in read mode.    
     
     
         2 . A memory according to  claim 1 , wherein said read select switch is arranged right under said memory cells.  
     
     
         3 . A memory according to  claim 1 , further comprising contact plugs each of which connects one terminal of one of said memory cells to said read select switch, and said contact plugs are overlapped each other.  
     
     
         4 . A memory according to  claim 1 , further comprising a source line that extends in the first direction and is connected to said read select switch.  
     
     
         5 . A memory according to  claim 4 , further comprising 
 a power supply terminal, and    a column select switch connected between said source line and said power supply terminal.    
     
     
         6 . A memory according to  claim 4 , further comprising a read word line which is connected to a control terminal of said read select switch and extends in a second direction perpendicular to the first direction.  
     
     
         7 . A memory according to  claim 6 , wherein said read select switch is controlled by a row address signal.  
     
     
         8 . A memory according to  claim 1 , further comprising a read word line which is connected to said read select switch and extends in a second direction perpendicular to the first direction.  
     
     
         9 . A memory according to  claim 8 , further comprising a decode line which is connected to a control terminal of said read select switch and extends in the first direction.  
     
     
         10 . A memory according to  claim 9 , wherein said read select switch is controlled by a column address signal.  
     
     
         11 . A memory according to  claim 1 , further comprising 
 a read circuit, and    a column select switch connected between said bit lines and said read circuit.    
     
     
         12 . A memory according to  claim 11 , wherein said read select switch and said column select switch execute the same operation.  
     
     
         13 . A memory according to  claim 11 , wherein said read circuit is constituted by sense amplifiers arranged in correspondence with said bit lines and output buffers arranged in correspondence with said sense amplifiers.  
     
     
         14 . A memory according to  claim 11 , wherein said read circuit is constituted by sense amplifiers arranged in correspondence with said bit lines, an output buffer which outputs one data of said sense amplifiers, and a selector which is connected between said sense amplifiers and said output buffer.  
     
     
         15 . A memory according to  claim 1 , further comprising a write bit line driver/sinker which is connected to two ends of each of said bit lines to flow, to said bit lines, a write current in a direction corresponding to write data.  
     
     
         16 . A memory according to  claim 1 , wherein said bit lines function as read bit lines and write bit lines.  
     
     
         17 . A memory according to  claim 1 , further comprising write word lines which are arranged in correspondence with said memory cells and extend in a second direction perpendicular to the first direction.  
     
     
         18 . A memory according to  claim 17 , wherein each of said write word lines is arranged on one terminal side of a corresponding one of said memory cells.  
     
     
         19 . A memory according to  claim 1 , further comprising block select switches each connected between the other terminal of a corresponding one of said memory cells and a corresponding one of said bit lines.  
     
     
         20 . A memory according to  claim 19 , wherein said block select switch is controlled by a row address signal.  
     
     
         21 . A memory according to  claim 19 , wherein said read select switch and said block select switch execute the same operation.  
     
     
         22 . A memory according to  claim 1 , wherein said memory cells construct one read block, and data of said memory cells are simultaneously read.  
     
     
         23 . A memory according to  claim 1 , wherein each of said memory cells is formed from a magnetic memory element including a pinning layer having a fixed magnetizing direction, a storing layer whose magnetizing direction changes in accordance with write data, and a tunneling barrier layer arranged between said pinning layer and said storing layer.  
     
     
         24 . A memory according to  claim 23 , wherein an axis of easy magnetization of said magnetic memory element is directed in a second direction perpendicular to the first direction.  
     
     
         25 . A memory according to  claim 1 , wherein said read select switch is formed from one of a MIS transistor, a MES transistor, a junction transistor, a bipolar transistor, and a diode.  
     
     
         26 . A magnetic random access memory comprising: 
 memory cells which are stacked at stages to store data using a magnetoresistive effect;    a read select switch which commonly connect to one terminal of each of said memory cells; and    bit lines which arrange in correspondence with said memory cells and extend in a first direction,    wherein each of said memory cells has the other terminal independently connected to one of said bit lines, and storing data of said memory cells are decided with according to directions of currents which flow in said bit lines.    
     
     
         27 . A memory according to  claim 26 , wherein said read select switch is arranged right under said memory cells.  
     
     
         28 . A memory according to  claim 26 , further comprising contact plugs each of which connects one terminal of one of said memory cells to said read select switch, and said contact plugs are overlapped each other.  
     
     
         29 . A memory according to  claim 26 , further comprising a source line that extends in the first direction and is connected to said read select switch.  
     
     
         30 . A memory according to  claim 29 , further comprising 
 a power supply terminal, and    a column select switch connected between said source line and said power supply terminal.    
     
     
         31 . A memory according to  claim 29 , further comprising a read word line which is connected to a control terminal of said read select switch and extends in a second direction perpendicular to the first direction.  
     
     
         32 . A memory according to  claim 31 , wherein said read select switch is controlled by a row address signal.  
     
     
         33 . A memory according to  claim 26 , further comprising a read word line which is connected to said read select switch and extends in a second direction perpendicular to the first direction.  
     
     
         34 . A memory according to  claim 33 , further comprising a decode line which is connected to a control terminal of said read select switch and extends in the first direction.  
     
     
         35 . A memory according to  claim 34 , wherein said read select switch is controlled by a column address signal.  
     
     
         36 . A memory according to  claim 26 , further comprising 
 a read circuit, and    a column select switch connected between said bit lines and said read circuit.    
     
     
         37 . A memory according to  claim 36 , wherein said read select switch and said column select switch execute the same operation.  
     
     
         38 . A memory according to  claim 36 , wherein said read circuit is constituted by sense amplifiers arranged in correspondence with said bit lines and output buffers arranged in correspondence with said sense amplifiers.  
     
     
         39 . A memory according to  claim 36 , wherein said read circuit is constituted by sense amplifiers arranged in correspondence with said bit lines, an output buffer which outputs one data of said sense amplifiers, and a selector which is connected between said sense amplifiers and said output buffer.  
     
     
         40 . A memory according to  claim 26 , further comprising a write bit line driver/sinker which is connected to two ends of each of said bit lines to flow, to said bit lines, a write current in a direction corresponding to write data.  
     
     
         41 . A memory according to  claim 26 , wherein said bit lines function as read bit lines and write bit lines.  
     
     
         42 . A memory according to  claim 26 , further comprising write word lines which are arranged in correspondence with said memory cells and extend in a second direction perpendicular to the first direction.  
     
     
         43 . A memory according to  claim 42 , wherein each of said write word lines is arranged on one terminal side of a corresponding one of said memory cells.  
     
     
         44 . A memory according to  claim 26 , further comprising block select switches each connected between the other terminal of a corresponding one of said memory cells and a corresponding one of said bit lines.  
     
     
         45 . A memory according to  claim 44 , wherein said block select switch is controlled by a row address signal.  
     
     
         46 . A memory according to  claim 44 , wherein said read select switch and said block select switch execute the same operation.  
     
     
         47 . A memory according to  claim 26 , wherein said memory cells construct one read block, and data of said memory cells are simultaneously read.  
     
     
         48 . A memory according to  claim 26 , wherein each of said memory cells is formed from a magnetic memory element including a pinning layer having a fixed magnetizing direction, a storing layer whose magnetizing direction changes in accordance with write data, and a tunneling barrier layer arranged between said pinning layer and said storing layer.  
     
     
         49 . A memory according to  claim 48 , wherein an axis of easy magnetization of said magnetic memory element is directed in a second direction perpendicular to the first direction.  
     
     
         50 . A memory according to  claim 26 , wherein said read select switch is formed from one of a MIS transistor, a MES transistor, a junction transistor, a bipolar transistor, and a diode.  
     
     
         51 . A magnetic random access memory comprising: 
 first and second memory cells which are stacked to store data using a magnetoresistive effect;    a read select switch which connect to one terminal of each of said first and second memories;    a first bit line which connect to the other terminal of said first memory cell; and    a second bit line which connect to the other terminal of said second memory cell,    wherein said first and second bit lines are electrically isolated each other in read mode.    
     
     
         52 . A magnetic random access memory comprising: 
 first and second memory cells which are stacked to store data using a magnetoresistive effect;    a read select switch which connect to one terminal of each of said first and second memories;    a first bit line which connect to the other terminal of said first memory cell; and    a second bit line which connect to the other terminal of said second memory cell,    wherein a storing data of said first memory cell is decided with according to a direction of a current which flows in said first bit line, and a storing data of said second memory cell is decided with according to a direction of a current which flows in said second bit line.    
     
     
         53 . A read method of a magnetic random access memory, the magnetic random access memory having a read block formed from memory cells which are stacked each other and which store data using a magnetoresistive effect, and sense amplifiers arranged in correspondence with the memory cells, comprising: 
 simultaneously and independently supplying a read current to the memory cells in the read block;    detecting data of the memory cells by the sense amplifiers on the basis of the read current; and    simultaneously outputting data of the sense amplifiers.    
     
     
         54 . A method according to  claim 53 , wherein the data of the memory cells are independently detected by the sense amplifiers.  
     
     
         55 . A method according to  claim 53 , wherein 
 the other terminal of each of the memory cells is short-circuited, and    the read current flows for one terminal side to the other terminal side of each of the memory cells.    
     
     
         56 . A method according to  claim 53 , wherein the sense amplifiers compare a read potential generated from the read current with a reference potential, thereby detecting the data of the memory cells.  
     
     
         57 . A method according to  claim 56 , wherein the reference potential is generated using a resistive element having the same structure as that of the memory cell.  
     
     
         58 . A method according to  claim 53 , wherein when the data of the memory cells are to be read, a ground potential is applied to one terminal of each of the memory cells.  
     
     
         59 . A method according to  claim 53 , wherein when the data of the memory cells are not to be read, one terminal of each of the memory cells is set in a short-circuited state, and the other terminal is set in a floating state.  
     
     
         60 . A read method of a magnetic random access memory, the magnetic random access memory having a read block formed from memory cells which are stacked each other and which store data using a magnetoresistive effect, and sense amplifiers arranged in correspondence with the memory cells, comprising: 
 simultaneously and independently supplying a read current to the memory cells in the read block;    detecting data of the memory cells by the sense amplifiers on the basis of the read current; and    selectively outputting one of data of the sense amplifiers.    
     
     
         61 . A method according to  claim 60 , wherein the data of the memory cells are independently detected by the sense amplifiers.  
     
     
         62 . A method according to  claim 60 , wherein 
 the other terminal of each of the memory cells is short-circuited, and    the read current flows for one terminal side to the other terminal side of each of the memory cells.    
     
     
         63 . A method according to  claim 60 , wherein the sense amplifiers compare a read potential generated from the read current with a reference potential, thereby detecting the data of the memory cells.  
     
     
         64 . A method according to  claim 63 , wherein the reference potential is generated using a resistive element having the same structure as that of the memory cell.  
     
     
         65 . A method according to  claim 60 , wherein when the data of the memory cells are to be read, a ground potential is applied to one terminal of each of the memory cells.  
     
     
         66 . A method according to  claim 60 , wherein when the data of the memory cells are not to be read, one terminal of each of the memory cells is set in a short-circuited state, and the other terminal is set in a floating state.  
     
     
         67 . A manufacturing method of a magnetic random access memory, comprising: 
 forming a read select switch on a surface region of a semiconductor substrate;    forming a first write word line extending in a first direction on the read select switch;    forming a first MTJ element right above the first write word line;    forming, right above the first MTJ element, a first read/write bit line which is in contact with the first MTJ element and extends in a second direction perpendicular to the first direction;    forming a second write word line extending in the first direction right above the first write word line;    forming a second MTJ element right above the second write word line; and    forming, right above the second MTJ element, a second read/write bit line which is in contact with the second MTJ element and extends in the second direction.    wherein, out of said first and second write word lines and said first and second read/write bit lines, at least metal lines under MTJs, are formed by a damascene process.    
     
     
         68 . A method according to  claim 67 , wherein, out of the first and second write word lines and the first and second read/write bit lines, at least metal lines under MTJS, are formed by steps of forming an interconnection trench in an insulating layer, forming a metal layer that completely fills the interconnection trench, and removing the metal layer except that in the interconnection trench.  
     
     
         69 . A method according to  claim 68 , further comprising, before formation of the metal layer, a step of forming a barrier metal layer.  
     
     
         70  A method according to  claim 69 , further comprising steps of, before formation of the barrier metal layer, forming a sidewall insulating layer on a side surface of the interconnection trench, and after removal of the metal layer except that in the interconnection trench, forming a cap insulating layer made of the same material as that of the sidewall insulating layer on the metal layer.  
     
     
         71 . A method according to  claim 70 , wherein the sidewall insulating layer and the cap insulating layer are made of silicon nitride.