US2003122253A1PendingUtilityA1

Wafer levelpackaging and chip structure

Priority: Dec 28, 2001Filed: Sep 12, 2002Published: Jul 3, 2003
Est. expiryDec 28, 2021(expired)· nominal 20-yr term from priority
Inventors:Chi-Hsing Hsu
H10W 72/9415H10W 72/942H10W 72/923H10W 72/922H10W 72/251H10W 70/655H10W 74/129H10W 72/019H10W 72/20
39
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A chip structure comprises a wafer, an insulation layer, some conductive paste, a plurality of ball pads, a solder mask and a plurality of solder balls. The wafer has an active surface. The insulation layer is formed over the active surface of the wafer. The insulation layer has a plurality of open windows. The conductive paste fills the open windows. The ball pads are formed over the insulation layer in electrical connection with the conductive paste. The solder mask formed over the insulation layer. The solder mask exposes the ball pads. A solder ball is mounted to each ball pad.

Claims

exact text as granted — not AI-modified
16 . A chip package structure, comprising: 
 a chip having an active side;    an insulation layer on the active side of the chip, wherein the insulation layer has a plurality of open windows that pass through the insulation layer;    a plurality of conductive paste plugs, wherein each of the conductive paste plugs is formed in the respective open window;    a patterned metallic layer with a plurality of ball pads on the insulation layer, wherein the ball pads are electrically connected to the conductive paste plugs;    a solder mask over the insulation layer to expose the ball pads; and    a plurality of solder balls, wherein each of the solder balls is mounted to the respective ball pad.    
     
     
         17 . The chip package structure of  claim 16 , wherein the structure further includes a redistribution circuit layer between the insulation layer and the chip, wherein the redistribution circuit layer comprises an insulation layer and a plurality of metallic circuit lines which criss-cross inside the insulation layer and connect electrically with the conductive paste plugs and the chip.  
     
     
         18 . The chip package structure of  claim 16 , wherein the structure also includes a plurality of bumps enclosed inside the open windows and connect electrically with the conductive paste plugs.  
     
     
         19 . An insulation structure having at least one conductive paste plug therein to be installed inside a chip package structure, comprising: 
 an insulation layer on the active side of a chip, wherein the insulation layer has at least one open window; and    conductive paste that completely filling the open window.    
     
     
         20 . The insulation structure of  claim 19 , wherein the structure further includes at least one bump inside the open window to connect electrically with the conductive paste.

Join the waitlist — get patent alerts

Track US2003122253A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.