Method of manufacturing a field effect transistor having a two-layered gate electrode

Abstract

A field effect transistor includes a lower gate electrode, upper gate electrode, first, second, and third barrier films, and source and drain. The lower gate electrode is formed from silicon on a silicon substrate via a gate insulating film. The upper gate electrode is formed from copper above the lower gate electrode. The first barrier film has a conductivity capable of supplying to the lower gate electrode a current enough to drive a channel portion, covers the lower surface of the upper gate electrode, and impedes diffusion of copper. The second barrier film has a lower end in contact with the first barrier film, covers the side surfaces of the upper gate electrode, and impedes diffusion of copper. The third barrier film has an end portion in contact with the second barrier film, covers the upper surface of the upper gate electrode, and impedes diffusion of copper. The source and drain are formed in the silicon substrate to sandwich a region under the lower gate electrode. A method of manufacturing the transistor is also disclosed.

What is claimed is:  
     
         1 . A field effect transistor comprising: 
 a lower gate electrode formed from silicon on a silicon substrate via a gate insulating film;    an upper gate electrode formed from copper above said lower gate electrode;    a first barrier film having a conductivity capable of supplying to said lower gate electrode a current enough to drive a channel portion and formed to cover a lower surface of said upper gate electrode and impede diffusion of copper;    a second barrier film having a lower end in contact with said first barrier film and formed to cover side surfaces of said upper gate electrode and impede diffusion of copper;    a third barrier film having an end portion in contact with said second barrier film and formed to cover an upper surface of said upper gate electrode and impede diffusion of copper; and    a source and drain formed in said silicon substrate to sandwich a region under said lower gate electrode.    
     
     
         2 . A transistor according to  claim 1 , wherein 
 said transistor further comprises an insulating film formed on said gate electrode,    said second barrier film extends on the side surfaces of said lower gate electrode, and    said second barrier film is formed from an insulating material having an etching rate lower than that of said insulating film under a predetermined etching condition.    
     
     
         3 . A transistor according to  claim 1 , wherein 
 said third barrier film is formed from an insulating material.    
     
     
         4 . A transistor according to  claim 3 , wherein 
 said transistor further comprises an insulating layer formed on said silicon substrate and having an opening on said upper gate electrode, and    said third barrier film extends on said insulating layer.    
     
     
         5 . A transistor according to  claim 3 , wherein 
 each of said second and third barrier films is formed from one of a refractory metal and a refractory metal nitride.    
     
     
         6 . A transistor according to  claim 1 , wherein 
 said first barrier film is formed from an insulating material having a thickness that allows a tunnel current to flow.    
     
     
         7 . A transistor according to  claim 1 , wherein 
 each of said first, second, and third barrier films is formed from one of a refractory metal and a refractory metal nitride.    
     
     
         8 . A transistor according to  claim 2 , wherein 
 the insulating material is one of silicon nitride and boron nitride.    
     
     
         9 . A method of manufacturing a field effect transistor, comprising at least the steps of: 
 forming a gate insulating film on a silicon substrate;    forming a lower gate electrode of silicon on said gate insulating film;    forming a sacrificial pattern on said lower gate electrode;    doping an impurity into a predetermined region of said silicon substrate using said lower gate electrode and said sacrificial pattern as a mask to form a source and drain;    forming a first interlayer insulating film of silicon oxide on said silicon substrate so as to cover said lower gate electrode and said sacrificial pattern;    removing said first interlayer insulating film to expose an upper surface of said sacrificial pattern;    selectively removing only said sacrificial pattern to expose an upper surface of said lower gate electrode and form a trench in said first interlayer insulating film on said lower gate electrode;    forming first and second barrier films having a conductivity for impeding diffusion of copper so as to cover the upper surface of said lower gate electrode and side surfaces of the trench;    forming an upper gate electrode of copper in the trench via said first and second barrier films such that bottom and side surfaces of said upper gate electrode are covered with said first and second barrier films; and    forming a third barrier film for impeding diffusion of copper so as to cover an exposed upper surface of said upper gate electrode.    
     
     
         10 . A method according to  claim 9 , wherein 
 said sacrificial pattern is formed from a material etched at a rate higher than that of silicon and silicon oxide under a predetermined etching condition.    
     
     
         11 . A method of manufacturing a field effect transistor, comprising at least the steps of: 
 forming a gate insulating film on a silicon substrate;    forming a lower gate electrode of silicon on said gate insulating film;    forming an etching stopper layer on said lower gate electrode;    forming a sacrificial pattern on said etching stopper layer;    doping an impurity into a predetermined region of said silicon substrate using said lower gate electrode and said sacrificial pattern as a mask to form a source and drain;    forming a first interlayer insulating film of silicon oxide on said silicon substrate so as to cover said lower gate electrode and said sacrificial pattern;    removing said first interlayer insulating film to expose an upper surface of said sacrificial pattern;    selectively removing said sacrificial pattern to expose an upper surface of said etching stopper layer;    removing said etching stopper layer to expose an upper surface of said lower gate electrode and form a trench on said lower gate electrode;    forming first and second barrier films having a conductivity for impeding diffusion of copper so as to cover the upper surface of said lower gate electrode and side surfaces of the trench;    forming an upper gate electrode of copper in the trench via said first and second barrier films such that bottom and side surfaces of said upper gate electrode are covered with said first and second barrier films; and    forming a third barrier film for impeding diffusion of copper so as to cover an exposed upper surface of said upper gate electrode.    
     
     
         12 . A method of manufacturing a field effect transistor, comprising at least the steps of: 
 forming a gate insulating film on a silicon substrate;    forming a lower gate electrode of silicon on said gate insulating film;    forming an etching stopper layer on said lower gate electrode;    forming a sacrificial pattern on said etching stopper layer;    doping an impurity into a predetermined region of said silicon substrate using said lower gate electrode and said sacrificial pattern as a mask to form a source and drain;    forming a first interlayer insulating film of silicon oxide on said silicon substrate so as to cover said lower gate electrode and said sacrificial pattern;    selectively removing said first interlayer insulating film to expose an upper surface of said sacrificial pattern and form a trench on said lower gate electrode;    selectively removing said sacrificial pattern to expose an upper surface of said etching stopper layer;    removing said etching stopper layer to expose an upper surface of said lower gate electrode;    forming first and second barrier films having a conductivity for impeding diffusion of copper so as to cover the upper surface of said lower gate electrode and side surfaces of the trench;    forming an upper gate electrode of copper in the trench via said first and second barrier films such that bottom and side surfaces of said upper gate electrode are covered with said first and second barrier films; and    forming a third barrier film for impeding diffusion of copper so as to cover an exposed upper surface of said upper gate electrode.    
     
     
         13 . A method according to  claim 12 , wherein 
 said sacrificial pattern is formed from a material etched at a rate higher than that of silicon oxide under a predetermined etching condition.    
     
     
         14 . A method according to  claim 9 , further comprising at least the steps of: 
 after the upper surface of said lower gate electrode is exposed, and the trench is formed, forming a refractory metal film;    forming a refractory metal nitride film on said refractory metal film;    forming a copper film; and    removing said copper film, said refractory metal film, and said refractory metal nitride film in a region other than the trench to form said upper gate electrode of copper and first and second barrier films formed from said refractory metal film and said refractory metal nitride film.    
     
     
         15 . A method according to  claim 9 , further comprising at least the steps of: 
 after the upper surface of said lower gate electrode is exposed, and the trench is formed, forming a first refractory metal film;    forming a refractory metal nitride film on said first refractory metal film;    forming a second refractory metal film on said refractory metal nitride film;    forming a copper film; and    removing said copper film, said first refractory metal film, said refractory metal nitride film, and said second refractory metal film in a region other than the trench to form said upper gate electrode of copper and first and second barrier films formed from said first refractory metal film, said refractory metal nitride film, and said second refractory metal film.    
     
     
         16 . A method according to  claim 14 , further comprising: 
 forming a refractory metal film in contact with said lower gate electrode; and    annealing said refractory metal film in contact with said lower gate electrode to form a refractory metal silicide film in contact with said lower gate electrode, said refractory metal silicide film serving as part of said first barrier film.    
     
     
         17 . A method of manufacturing a field effect transistor, comprising at least the steps of: 
 forming a gate insulating film on a silicon substrate;    forming a lower gate electrode of silicon on said gate insulating film;    forming a sacrificial pattern on said lower gate electrode;    doping an impurity into a predetermined region of said silicon substrate using said lower gate electrode and said sacrificial pattern as a mask to form a source and drain;    forming a side wall of an insulating material for impeding diffusion of copper on side surfaces of said lower gate electrode and said sacrificial pattern;    forming a first interlayer insulating film of silicon oxide on said silicon substrate so as to cover said lower gate electrode and said sacrificial pattern;    removing said first interlayer insulating film to expose an upper surface of said sacrificial pattern;    selectively removing said sacrificial pattern to form a trench on said lower gate electrode;    forming a first barrier film having a conductivity for impeding diffusion of copper so as to cover the upper surface of said lower gate electrode and make two ends of said first barrier film in contact with said side wall;    forming an upper gate electrode of copper in the trench via said first barrier film so that a bottom surface of said upper gate electrode is covered with said first barrier film and two side surfaces of said upper gate electrode are covered with a second barrier film formed from said side wall; and    forming a third barrier film for impeding diffusion of copper so as to cover an exposed upper surface of said upper gate electrode.    
     
     
         18 . A method of manufacturing a field effect transistor, comprising at least the steps of: 
 forming a gate insulating film on a silicon substrate;    forming a lower gate electrode of silicon on said gate insulating film;    forming an etching stopper layer on said lower gate electrode;    forming a sacrificial pattern on said etching stopper layer;    doping an impurity into a predetermined region of said silicon substrate using said lower gate electrode and said sacrificial pattern as a mask to form a source and drain;    forming a side wall of an insulating material for impeding diffusion of copper on two side surfaces of said lower gate electrode, said etching stopper layer, and said sacrificial pattern;    forming a first interlayer insulating film of silicon oxide on said silicon substrate so as to cover said lower gate electrode, said etching stopper layer, and said sacrificial pattern;    removing said first interlayer insulating film to expose an upper surface of said sacrificial pattern;    selectively removing said sacrificial pattern to expose an upper surface of said etching stopper layer;    removing said etching stopper layer to form a trench on said lower gate electrode;    forming a first barrier film having a conductivity for impeding diffusion of copper so as to cover in contact with the upper surface of said lower gate electrode and make two ends of said first barrier film in contact with said side wall;    forming an upper gate electrode of copper in the trench via said first barrier film so that a bottom surface of said upper gate electrode is covered with said first-barrier film and two side surfaces of said upper gate electrode are covered with a second barrier film formed from said side wall; and    forming a third barrier film for impeding diffusion of copper so as to cover an exposed upper surface of said upper gate electrode.    
     
     
         19 . A method of manufacturing a field effect transistor, comprising at least the steps of: 
 forming a gate insulating film on a silicon substrate;    forming a lower gate electrode of silicon on said gate insulating film;    forming an etching stopper layer on said lower gate electrode;    forming a sacrificial pattern on said etching stopper layer;    doping an impurity into a predetermined region of said silicon substrate using said lower gate electrode and said sacrificial pattern as a mask to form a source and drain;    forming a side wall of an insulating material for impeding diffusion of copper on two side surfaces of said lower gate electrode, said etching stopper layer, and said sacrificial pattern;    forming a first interlayer insulating film of silicon oxide on said silicon substrate so as to cover said lower gate electrode, said etching stopper layer, and said sacrificial pattern;    selectively removing said first interlayer insulating film to expose an upper surface of said sacrificial pattern and form a trench on said lower gate electrode;    selectively removing said sacrificial pattern to expose an upper surface of said etching stopper layer;    removing said etching stopper layer;    forming a first barrier film having a conductivity for impeding diffusion of copper so as to cover in contact with the upper surface of said lower gate electrode and make two ends of said first barrier film in contact with said side wall;    forming an upper gate electrode of copper in the trench via said first barrier film so that a bottom surface of said upper gate electrode is covered with said first barrier film and two side surfaces of said upper gate electrode are covered with a second barrier film formed from said side wall; and    forming a third barrier film for impeding diffusion of copper so as to cover an exposed upper surface of said upper gate electrode.    
     
     
         20 . A method according to  claim 17 , wherein 
 said side wall is formed from a silicon nitride.    
     
     
         21 . A method according to  claim 9 , wherein 
 said first barrier film is formed by nitriding the upper surface of said lower gate electrode to a thickness that allows a tunnel current to flow.    
     
     
         22 . A method according to  claim 9 , wherein 
 said first or second barrier film is formed by increasing particles incident on a bottom surface of the trench at an angle of 90° or at an angle close to 90°.    
     
     
         23 . A transistor according to  claim 1 , wherein 
 said first barrier film is a multilayered film having at least two layers.    
     
     
         24 . A transistor according to  claim 1 , wherein 
 said first barrier film is a multilayered film having one of combinations of a plurality of refractory metal layers, refractory metal silicide layers, layers of a compound of a refractory metal, silicon, and nitride, and refractory metal nitride layers.    
     
     
         25 . A transistor according to  claim 23 , wherein 
 said first barrier film is a multilayered film in which a lowermost layer is formed from a layer of a metal silicide or a compound of a refractory metal, silicon, and nitride.    
     
     
         26 . A transistor according to  claim 25 , wherein 
 said first barrier film is a multilayered film in which a lowermost layer is formed from a layer of a metal silicide or a compound of a refractory metal, silicon, and nitride, and a refractory metal nitride layer is stacked on said metal silicide layer.    
     
     
         27 . A transistor according to  claim 25 , wherein 
 said first barrier film is a multilayered film in which a lowermost layer is formed from a layer of a metal silicide or a compound of a refractory metal, silicon, and nitride, a refractory metal nitride layer is stacked on said metal silicide layer, and an uppermost layer is formed from a refractory metal.    
     
     
         28 . A transistor according to  claim 1 , wherein 
 a refractory metal silicide film is formed on said source and drain.    
     
     
         29 . A method according to  claim 9 , wherein 
 said sacrificial layer, said etching stopper film, and said lower gate electrode are processed using a hard mask.    
     
     
         30 . A method according to  claim 11 , wherein 
 said sacrificial layer, said etching stopper film, and said lower gate electrode are processed using a hard mask formed from silicon oxide or silicon nitride.    
     
     
         31 . A method according to  claim 9 , wherein 
 a refractory metal silicide is formed in predetermined regions of said source and drain before formation of said upper gate electrode.    
     
     
         32 . A transistor according to  claim 3 , wherein 
 the insulating material is one of silicon nitride and boron nitride.    
     
     
         33 . A transistor according to  claim 4 , wherein 
 the insulating material is one of silicon nitride and boron nitride.    
     
     
         34 . A transistor according to  claim 5 , wherein 
 the insulating material is one of silicon nitride and boron nitride.    
     
     
         35 . A transistor according to  claim 6 , wherein 
 the insulating material is one of silicon nitride and boron nitride.    
     
     
         36 . A method according to  claim 14 , further comprising at least the steps of: 
 forming a refractory metal film in contact with said lower gate electrode; and    annealing said refractory metal film in contact with said lower gate electrode to form a refractory metal silicide film in contact with said lower gate electrode, said refractory metal silicide film serving as part of said first barrier film.    
     
     
         37 . A method according to  claim 17 , wherein 
 said sacrificial layer, said etching stopper film, and said lower gate electrode are processed using a hard mask formed from silicon oxide or silicon nitride.    
     
     
         38 . A method according to  claim 22 , wherein 
 said sacrificial layer, said etching stopper film, and said lower gate electrode are processed using a hard mask formed from silicon oxide or silicon nitride.    
     
     
         39 . A method according to  claim 14 , wherein 
 said sacrificial layer, said etching stopper film, and said lower gate electrode are processed using a hard mask formed from silicon oxide or silicon nitride.    
     
     
         40 . A method according to  claim 9 , further comprising at least the steps of: 
 after the upper surface of said lower gate electrode is exposed, and the trench is formed, forming a film of a compound of a refractory metal, silicon, and nitrogen;    forming a refractory metal nitride film on said film of the compound of the refractory metal, silicon, and nitrogen;    forming a copper film as said upper gate electrode; and    removing said copper film, said refractory metal film, and said refractory metal nitride film in a region other than the trench to form said upper gate electrode of copper and first and second barrier films formed from said refractory metal film and said refractory metal nitride film.    
     
     
         41 . A method according to  claim 9 , further comprising at least the steps of: 
 after the upper surface of said lower gate electrode is exposed, and the trench is formed, forming a film of a compound of a refractory metal, silicon, and nitrogen;    forming a refractory metal nitride film on said film of the compound of the refractory metal, silicon, and nitrogen;    forming a refractory metal film on said refractory metal nitride film;    forming a copper film as said upper gate electrode; and    removing said copper film, said first refractory metal film, said refractory metal nitride film, and said second refractory metal film in a region other than the trench to form said upper gate electrode of copper and first and second barrier films formed from said first refractory metal film, said refractory metal nitride film, and said second refractory metal film.    
     
     
         42 . A method according to  claim 17 , further comprising at least the steps of: 
 forming a refractory metal film in contact with said lower gate electrode;    annealing said refractory metal film in contact with said lower gate electrode to react said refractory metal film with silicon to a film of a compound of a refractory metal, silicon, and nitrogen in contact with said lower gate electrode, said film of the compound of the refractory metal, silicon, and nitrogen serving as part of said first barrier film.