Method of generating asic design database

Abstract

When a function design has been carried out by an RTL description using an HDL language, a CPU of an integrated circuit design support apparatus writes data such as a simulation time, a layout area, a timing and a power consumption into a header portion of the RTL description. The CPU stores, as one file, the RTL description comprising the header portion serving as a reuse design database, and an entity portion, in a hard disk drive.

What is claimed is:  
     
         1 . A method of generating an ASIC design database, comprising: 
 extracting, when a function design using description data comprising a header portion and an entity portion has been performed, information necessary for reuse design from various execution results of the entity portion;    writing the extracted information necessary for reuse design in the header portion of the description data; and    storing, as one file at a predetermined location, the description data comprising the header portion in which the information necessary for reuse is written, and the entity portion.    
     
     
         2 . A method of generating an ASIC design database, according to  claim 1 , wherein the information necessary for reuse, which is extracted from the various execution results of the entity portion, is at least a simulation time, layout area, timing, and power consumption.  
     
     
         3 . A method of generating an ASIC design database, according to  claim 1 , wherein the entity portion of said description data is described using a hardware description language.  
     
     
         4 . A method of generating an ASIC design database, according to  claim 1 , wherein the entity portion of said description data is RTL description data described in a register transfer level.  
     
     
         5 . A method of generating an ASIC design database, according to  claim 1 , wherein in the file stored at the predetermined location, information written in the header portion and RTL description data in the entity portion are uniformly managed.  
     
     
         6 . A method of generating an ASIC design database, comprising: 
 extracting, when a function design using RTL description data comprising a header portion and an entity portion and made in a register transfer level has been performed, information necessary for reuse design from various execution results of the entity portion;    writing the extracted information necessary for reuse design in the header portion of the RTL description data; and    storing, as one file at a predetermined location, the RTL description data comprising the header portion in which the information necessary for reuse is written, and the entity portion.    
     
     
         7 . A method of generating an ASIC design database, comprising: 
 performing, when a function design has been carried out by an RTL description composed of a header portion and an entity portion and made in a register transfer level, a simulation using a simulation tool with respect to the entity portion of the RTL description;    extracting a simulation time from a simulation result and writing the simulation time in the header portion of the RTL description;    inputting the entity portion of the RTL description to a logic synthesis tool and logic-synthesizing the entity portion, and outputting a gate-level net list;    inputting the output gate-level net list to a timing analysis tool, and outputting a timing analysis result report;    comparing values of the timing analysis result report with preset conditions;    extracting a timing value and a layout area information, which are the result of the analysis, when said conditions are met, and writing the extracted timing value and layout area information in the header portion of the RTL description;    performing a logic simulation using a logic simulation tool with respect to the gate-level net list;    inputting data of the logic simulation to a power consumption calculation tool, and outputting a power consumption calculation result;    extracting a power consumption from the power consumption calculation result, and writing the power consumption in the header portion of the RTL description; and    storing, as one file at a predetermined location, the RTL description comprising the header portion in which the simulation time, the timing value, the layout area information and the power consumption are written, and the entity portion.