Power generator circuit, generating method thereof, and liquid crystal display device

Abstract

A power generator circuit, generation method, and liquid crystal display (LCD) wherein the power generator circuit does not require the design of a set when a negative or positive power generator circuit is installed outside the LCD panel. In a liquid crystal display integrated-with-drive circuit, a positive or negative power generator circuit is incorporated into the LCD panel and supplies a positive or negative voltage to a vertical driver circuit.

What is claimed is:  
     
         1 . A power generator circuit comprising: 
 first clamping means to clamp the high level or low level of a clock pulse having a phase opposite the phase of the input clock to a reference voltage within ground level or to a positive reference voltage;    second clamping means to clamp the high level or low level of a clock pulse having a positive phase versus the input clock phase to a reference voltage within ground level or to a positive reference voltage level; and    sampling means to sample the high level or low level of the clamped output of the first clamping means, and the high level or low level of the clamped output of the second clamping means.    
     
     
         2 . A power generator circuit as claimed in  claim 1  wherein said power generator circuit has a first and second condenser in the pre-stage of said first and said second clamping means to cut the respective direct current components of said reverse phase clock and said positive phase clock.  
     
     
         3 . A power generator circuit as claimed in  claim 1  wherein said power generator circuit has a fixed voltage means connected between the output end of said sampling means and a point at the reference voltage within ground level or a point at a positive reference voltage level.  
     
     
         4 . A power generator circuit as claimed in  claim 1  wherein said first clamping means performs clamping based on the input clock of said second clamping means, and said second clamping means performs clamping based on the input clock of said first clamping means.  
     
     
         5 . A power generator circuit as claimed in  claim 1  wherein said first and said second clamping means perform clamping based on their own respective input clocks.  
     
     
         6 . A power generation method wherein the high level or the low level of the positive phase or reverse phase of each clock with respect to the input clock is clamped at a reference voltage level within ground level or a positive reference voltage level and, the low level or the high level of the clamped positive phase clock is sampled at the high level or the low level of the clamped reverse phase clock.  
     
     
         7 . A power generation method as claimed in  claim 6  wherein the respective direct current components of said forward and reverse phase clocks are cut prior to clamping of said forward and reverse phase clock.  
     
     
         8 . A liquid crystal display device having a pixel area and at least a drive circuit containing a vertical driver integrated onto the same board of polysilicon wherein, the power generator circuit for generating the power supply voltage is incorporated onto said board.  
     
     
         9 . A liquid crystal display device as claimed in  claim 8  wherein said power generator circuit supplies the generated power supply voltage to said drive circuit.  
     
     
         10 . A liquid crystal display device as claimed in  claim 9  wherein said power generator circuit supplies the generated power supply voltage to said vertical driver.  
     
     
         11 . A liquid crystal display device as claimed in  claim 10  wherein said power generator circuit generates a power supply voltage based on a clock at a frequency higher than the vertical clock utilizing said vertical driver.  
     
     
         12 . A liquid crystal display device as claimed in  claim 11  wherein said power generator circuit generates a power supply voltage based on a horizontal clock utilizing a horizontal driver containing said driver circuit.  
     
     
         13 . A liquid crystal display device as claimed in  claim 9  wherein said drive circuit has a sampling latch circuit to synchronize the digital data with the horizontal scanning and perform sequential sample latching, a relatch circuit to perform re-latching at 1H (H is horizontal scanning period) periods of data latched by the sampling latch circuit, a level shifter to convert the level of the data re-latched by the latch circuit, a DA (digital/analog) converter to receive the data level-converted by the level shifter and select the desired reference voltage from among several contrast (gradient) reference voltages and output the selected reference voltage; and said power generator circuit supplies the generated power supply voltage to said level shifter.  
     
     
         14 . A liquid crystal display device as claimed in  claim 8  wherein said power generator circuit has a first clamping means to clamp the high level or low level of a clock pulse having a phase opposite the phase of the input clock to a reference voltage within ground level or to a positive reference voltage, a second clamping means to clamp the high level or low level of a clock pulse having a positive phase versus the input clock phase to a reference voltage within ground level or to a positive reference voltage level, and a sampling means to sample the high level or low level of the clamped output of the first clamping means, and the high level or low level of the clamped output of the second clamping means.  
     
     
         15 . A liquid crystal display device as claimed in  claim 14  wherein said power generator circuit has a first and second condenser in the pre-stage of said first and said second clamping means to cut the respective direct current components of said reverse phase clock and said positive phase clock.  
     
     
         16 . A liquid crystal display device as claimed in  claim 14  wherein said power generator circuit has a fixed voltage means connected between the output end of said sampling means and a point at the reference voltage within ground level or a point at a positive reference voltage level.  
     
     
         17 . A liquid crystal display device as claimed in  claim 8  wherein said first clamping means performs clamping based on the input clock of said second clamping means, and said second clamping means performs clamping based on the input clock of said first clamping means.  
     
     
         17 . A liquid crystal display device as claimed in  claim 8  wherein said first and said second clamping means perform clamping based on their own respective input clocks.