Semiconductor device and its manufacturing method capable of reducing low frequency noise

Abstract

In a semiconductor device, a first semiconductor layer is formed on a semiconductor substrate. A second semiconductor layer is formed on a part of the first semiconductor layer, and a third semiconductor layer is formed on a part of the second semiconductor layer. A first electrode is formed on the third semiconductor layer, and a second electrode is formed on the first semiconductor layer in contact with the second semiconductor layer and apart from the semiconductor layer, thus forming a diode.

1 . A semiconductor device comprising: 
 a semiconductor substrate;    a first semiconductor layer formed on said semiconductor substrate;    a second semiconductor layer formed on a part of said first semiconductor layer;    a third semiconductor layer formed on a part of said second semiconductor layer;    a first electrode formed on said third semiconductor layer; and    a second electrode formed on said first semiconductor layer in contact with said second semiconductor layer and apart from said third semiconductor layer;    thus forming a diode.    
     
     
         2 . The semiconductor device as set forth in  claim 1 , wherein said first and third semiconductor layers are of one conductivity type, and said second semiconductor layer is undoped, so that said diode is a Schottky barrier diode.  
     
     
         3 . The semiconductor device as set forth in  claim 1 , wherein said first, second and third semiconductor layers are of one conductivity type, so that said diode is a Schottky barrier diode.  
     
     
         4 . The semiconductor device as set forth in  claim 1 , wherein said first and third semiconductor layers have a different material from that of said second semiconductor layer.  
     
     
         5 . The semiconductor device as set forth in  claim 1 , wherein said second electrode is buried in said first semiconductor layer.  
     
     
         6 . The semiconductor device as set forth in  claim 1 , further comprising: 
 a fourth semiconductor layer formed on said second semiconductor layer; and    a fifth semiconductor layer formed on said fourth semiconductor layer,    said second and fifth semiconductor layers being made of a material different from that of said first, third and fourth semiconductor layers.    
     
     
         7 . The semiconductor device as set forth in  claim 1 , further comprising a fourth semiconductor layer formed on said third semiconductor layer, 
 said first and third semiconductor layers being of a first conductivity type, said fourth semiconductor layer being a second conductivity type opposite to said first conductivity type, so that said diode is a tunnel diode.    
     
     
         8 . The semiconductor device as set forth in  claim 6 , wherein said second semiconductor layer is undoped.  
     
     
         9 . The semiconductor device as set forth in  claim 6 , wherein said second semiconductor layer is of said first conductivity type.  
     
     
         10 . The semiconductor device as set forth in  claim 1 , further comprising: 
 a fourth semiconductor layer of an i-type conductivity type formed on said third semiconductor layer; and    a fifth semiconductor layer formed on said fourth semiconductor layer,    said first and third semiconductor layers being of a first conductivity type, said fifth semiconductor layer being of a second conductivity type opposite to said first conductivity type, so that said diode is a PIN diode.    
     
     
         11 . The semiconductor device as set forth in  claim 10 , wherein said second semiconductor layer is undoped.  
     
     
         12 . The semiconductor device as set forth in  claim 10 , wherein said second semiconductor layer is of said first conductivity type.  
     
     
         13 . The semiconductor device as set forth in  claim 1 , further comprising: 
 an i-type channel layer between said semiconductor substrate and said first semiconductor layer; and    a charge supply layer formed between said i-type channel layer and said first semiconductor layer,    said i-type channel layer, said charge supply layer and said first semiconductor layer forming a heterojunction field effect transistor separated from said diode.    
     
     
         14 . The semiconductor device as set forth in  claim 13 , wherein said diode and said field effect transistor are separated by an isolation region therebetween in said i-type channel layer and said charge supply layer.  
     
     
         15 . The semiconductor device as set forth in  claim 1 , further comprising; 
 a semiconductor base layer having a conductivity type opposite to that of said third semiconductor layer formed on said third semiconductor layer;    a semiconductor emitter layer having the same conductivity type as that of said third semiconductor layer formed on said semiconductor base layer; and    a semiconductor emitter cap layer having the same conductivity type as that of said third semiconductor layer formed on said semiconductor emitter layer;    said first, second and third semiconductor layers, said semiconductor base layer, said semiconductor emitter layer and said semiconductor emitter cap layer forming a heterojunction bipolar transistor separated from said diode.    
     
     
         16 . The semiconductor device as set forth in  claim 15 , wherein said diode and said bipolar transistor are separated by a groove formed in said first semiconductor layer and said semiconductor substrate.  
     
     
         17 . A semiconductor device comprising: 
 a semiconductor substrate;    a first semiconductor layer formed on said semiconductor substrate;    a second semiconductor layer formed on a part of said first semiconductor layer;    a first electrode formed on said second semiconductor layer; and    a second electrode buried in said first semiconductor layer and apart from said second semiconductor layer,    thus forming a diode.    
     
     
         18 . The semiconductor device as set forth in  claim 17 , wherein said first and second semiconductor layers are of one conductivity type, so that said diode is a Schottky barrier diode.  
     
     
         19 . The semiconductor device as set forth in  claim 17 , further comprising: 
 a third semiconductor layer formed on said first semiconductor layer; and    a fourth semiconductor layer formed on said third semiconductor layer,    said second and fourth semiconductor layers being made of a material different from that of said first, second and third semiconductor layers.    
     
     
         20 . The semiconductor device as set forth in  claim 17 , further comprising a third semiconductor layer formed on said second semiconductor layer, 
 said first and second semiconductor layers being of a first conductivity type, said third semiconductor layer being a second conductivity type opposite to said first conductivity type, so that said diode is a tunnel diode.    
     
     
         21 . The semiconductor device as set forth in  claim 17 , further comprising: 
 a third semiconductor layer of an i-type conductivity type second on said second semiconductor layer; and    a fourth semiconductor layer formed on said third semiconductor layer,    said first and second semiconductor layers being of a first conductivity type, said fourth semiconductor layer being of a second conductivity type opposite to said first conductivity type, so that said diode is a PIN diode.    
     
     
         22 . The semiconductor device as set forth in  claim 17 , further comprising: 
 an i-type channel layer between said semiconductor substrate and said first semiconductor layer; and    a charge supply layer formed between said i-type channel layer and said first semiconductor layer,    said i-type channel layer, said charge supply layer and said first semiconductor layer forming a heterojunction field effect transistor separated from said diode.    
     
     
         23 . The semiconductor device as set forth in  claim 22 , wherein said diode and said field effect transistor are separated by an isolation region therebetween in said i-type channel layer and said charge supply layer.  
     
     
         24 . The semiconductor device as set forth in  claim 17 , further comprising: 
 a semiconductor base layer having a conductivity type opposite to that of said third semiconductor layer formed on said second semiconductor layer;    a semiconductor emitter layer having the same conductivity type as that of said second semiconductor layer formed on said semiconductor base layer; and    a semiconductor emitter cap layer having the same conductivity type as that of said second semiconductor layer formed on said semiconductor emitter layer,    said first and second semiconductor layers, said semiconductor base layer, said semiconductor emitter layer and said semiconductor emitter cap layer forming a heterojunction bipolar transistor separated from said diode.    
     
     
         25 . The semiconductor device as set forth in  claim 24 , wherein said diode and said bipolar transistor are separated by a groove formed in said first semiconductor layer and said semiconductor substrate.  
     
     
         26 . A method for manufacturing a semiconductor device, comprising the steps of: 
 forming first, second and third semiconductor layers on a semiconductor substrate by an epitaxial growing process;    patterning said third semiconductor layer by an etching process using said second semiconductor layer as an etching stopper;    patterning said second semiconductor layer by an etching process using said first semiconductor layer as an etching stopper, so that said third semiconductor layer is formed on a part of said second semiconductor layer;    forming a first electrode on said third semiconductor layer; and    forming a second electrode on said first semiconductor layer adjacent to said second semiconductor layer and apart from said third semiconductor layer,    thus completing a diode.    
     
     
         27 . The method as set forth in  claim 26 , wherein said first and third semiconductor layers are of one conductivity type, and said second semiconductor layer is undoped, so that said diode is a Schottky barrier diode.  
     
     
         28 . The method as set forth in  claim 26 , wherein said first, second and third semiconductor layers are of one conductivity type, so that said diode is a Schottky barrier diode.  
     
     
         29 . The method as set forth in  claim 26 , wherein said first and third semiconductor layers have a different material from that of said second semiconductor layer.  
     
     
         30 . The method as set forth in  claim 27 , further comprising a step of partly etching said first semiconductor layer after said second semiconductor layer is patterned and before said second electrode is formed, so that said second electrode is buried in said first semiconductor layer.  
     
     
         31 . The method as set forth in  claim 27 , wherein said epitaxial growing step further forms a fourth semiconductor layer and a fifth semiconductor layer between said second and fourth semiconductor layers, 
 said second and fifth semiconductor layers being made of a material different from that of said first, third and fourth semiconductor layers.    
     
     
         32 . The method as set forth in  claim 27 , wherein said epitaxial growing step further forms a fourth semiconductor layer on said third semiconductor layer, 
 said first and third semiconductor layers being of a first conductivity type, said fourth semiconductor layer being a second conductivity type opposite to said first conductivity type, so that said diode is a tunnel diode.    
     
     
         33 . The method as set forth in  claim 31 , wherein said second semiconductor layer is undoped.  
     
     
         34 . The method as set forth in  claim 31 , wherein said second semiconductor layer is of said first conductivity type.  
     
     
         35 . The method as set forth in  claim 26 , wherein said epitaxial growing step further forms a fourth semiconductor layer of an i-type conductivity type and a fifth semiconductor layer on said fourth semiconductor layer, 
 said first and third semiconductor layers being of a first conductivity type, said fifth semiconductor layer being of a second conductivity type opposite to said first conductivity type, so that said diode is a PIN diode.    
     
     
         36 . The method as set forth in  claim 35 , wherein said second semiconductor layer is undoped.  
     
     
         37 . The method as set forth in  claim 35 , wherein said second semiconductor layer is of said first conductivity type.  
     
     
         38 . The method as set forth in  claim 26 , wherein said epitaxial growing step further forms an i-type channel layer and a charge supply layer between said semiconductor substrate and said first semiconductor layer, 
 said i-type channel layer, said charge supply layer and said first semiconductor layer forming a heterojunction field effect transistor separated from said diode.    
     
     
         39 . The method as set forth in  claim 38 , further comprising a step of forming an isolation region in said i-type channel layer and said charge supply layer, so that said diode and said field effect transistor are separated by said isolation region.  
     
     
         40 . The method as set forth in  claim 26 , wherein said epitaxial growing step further forms a semiconductor base layer having a conductivity type opposite to that of said third semiconductor layer; 
 a semiconductor emitter layer having the same conductivity type as that of said third semiconductor layer, and a semiconductor emitter cap layer having the same conductivity type as that of said third semiconductor layer on said third semiconductor layer;    said first, second and third semiconductor layers, said semiconductor base layer, said semiconductor emitter layer and said semiconductor emitter cap layer forming a heterojunction bipolar transistor separated from said diode.    
     
     
         41 . The method as set forth in  claim 40 , further comprising a step of forming a groove in said first semiconductor layer and said semiconductor substrate, so that said diode and said bipolar transistor are separated by said groove.  
     
     
         42 . A method for manufacturing a semiconductor device, comprising the steps of: 
 forming first and second semiconductor layers on a semiconductor substrate by an epitaxial growing process substrate;    patterning said second semiconductor layer so that said second semiconductor layer is formed on a part of said first semiconductor layer;    partly etching said first semiconductor layer after said second semiconductor layer is patterned;    forming a first electrode on said second semiconductor layer; and    burying a second electrode in said first semiconductor layer and apart from said second semiconductor layer,    thus forming a diode.    
     
     
         43 . The method as set forth in  claim 32 , wherein said first and second semiconductor layers are of one conductivity type, so that said diode is a Schottky barrier diode.  
     
     
         44 . The method as set forth in  claim 42 , wherein said epitaxial growing step further forms a third semiconductor layer and a fourth semiconductor layer between said first and third semiconductor layers, 
 said third semiconductor layer being made of a material different from that of said first and second semiconductor layers.    
     
     
         45 . The method as set forth in  claim 42 , wherein said epitaxial process further forms a third semiconductor layer on said second semiconductor layer, 
 said first and second semiconductor layers being of a first conductivity type, said third semiconductor layer being a second conductivity type opposite to said first conductivity type, so that said diode is a tunnel diode.    
     
     
         46 . The method as set forth in  claim 42 , wherein said epitaxial growing step further forms a third semiconductor layer of an i-type conductivity type and a fourth semiconductor layer on said second semiconductor layer, 
 said first and second semiconductor layers being of a first conductivity type, said fourth semiconductor layer being of a second conductivity type opposite to said first conductivity type, so that said diode is a PIN diode.    
     
     
         47 . The method as set forth in  claim 42 , wherein said epitaxial growing step further forms an i-type channel layer and a charge supply layer between said first semiconductor substrate and said first semiconductor layer, 
 said i-type channel layer, said charge supply layer and said first semiconductor layer forming a field effect transistor having hetero junctions separated from said diode.    
     
     
         48 . The method as set forth in  claim 47 , further comprising a step of forming an isolation region in said i-type channel layer and said charge supply layer, so that said diode and said field effect transistor are separated by said isolation region.  
     
     
         49 . The method as set forth in  claim 42 , wherein said epitaxial growing step further forms a semiconductor base layer having a conductivity type opposite to that of said third semiconductor layer, a semiconductor emitter layer having the same conductivity type as that of said second semiconductor layer, and a semiconductor emitter cap layer having the same conductivity type as that of said second semiconductor layer on said second semiconductor layer, 
 said first and second semiconductor layers, said semiconductor base layer, said semiconductor emitter layer and said semiconductor emitter cap layer forming a heterojunction bipolar transistor separated from said diode.    
     
     
         50 . The method as set forth in  claim 49 , further comprising a step of forming a groove formed in said first semiconductor layer and said semiconductor substrate, so that said diode and said bipolar transistor are separated by said groove.