Non-volatile memory device with improved data retention and method therefor

Abstract

A semiconductor device ( 30 ) comprises an underlying insulating layer ( 34 ), an overlying insulating layer ( 42 ) and a charge storage layer ( 36 ) between the insulating layers ( 34, 42 ). The charge storage layer ( 36 ) and the overlying insulating layer ( 42 ) form an interface, where at least a majority of charge in the charge storage layer ( 36 ) is stored. This can be accomplished by forming a charge storage layer ( 36 ) with different materials such as silicon and silicon germanium layers or n-type and p-type material layers, in one embodiment. In another embodiment, the charge storage layer ( 36 ) comprises a dopant that is graded. By storing at least a majority of the charge at the interface between the charge storage layer ( 36 ) and the overlying insulating layer ( 42 ), the leakage of charge through the underlying insulating layer is decreased allowing for a thinner underlying insulating layer ( 34 ) to be used.

What is claimed is:  
     
         1 . A semiconductor device comprising: 
 a semiconductor substrate;    a first insulating layer formed over the semiconductor substrate;    a charge storage layer formed over the first insulating layer comprising: 
 a plurality of charge,  
   a second insulating layer formed on the charge storage layer, wherein the second insulating layer and the charge storage layer form a first interface and at least a majority of the plurality of charge is stored substantially at the first interface; and    a conductive layer formed over the second insulating layer.    
     
     
         2 . The semiconductor device of  claim 1 , wherein the charge storage layer comprises two layers.  
     
     
         3 . The semiconductor device of  claim 2 , wherein the charge storage layer further comprises: 
 a first layer comprising silicon;    a second layer over the first layer, in physical contact with the second insulating layer, and comprising silicon and germanium.    
     
     
         4 . The semiconductor device of  claim 2 , wherein the charge storage layer further comprises: 
 a first layer comprising a first doped material;    a second layer over the first layer, in physical contact with the second insulating layer, and comprising a second doped material, wherein the second doped material is of opposite conductivity than the first doped material.    
     
     
         5 . The semiconductor device of  claim 2 , wherein the charge storage layer further comprises: 
 a first layer formed over the first insulating layer comprising jet vapor deposited silicon nitride; and    a second layer formed over the first layer comprising chemical vapor deposited silicon nitride.    
     
     
         6 . The semiconductor device of  claim 1 , wherein the charge storage layer comprises dopants which comprise: 
 a first concentration in a first portion of the charge storage layer; and    a second concentration in a second portion of the charge storage layer, wherein the second portion of the charge storage layer is in contact with the second insulating layer and the second concentration is greater than the first concentration.    
     
     
         7 . The semiconductor device of  claim 1 , wherein the plurality of charge are electrons.  
     
     
         8 . The semiconductor device of  claim 1 , wherein the charge storage layer is in physical contact with the first insulating layer and forms a second interface, wherein none of the plurality of charge is stored at the second interface.  
     
     
         9 . The semiconductor device of  claim 1 , wherein the semiconductor device is a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) device.  
     
     
         10 . The semiconductor device of  claim 1 , wherein the charge storage layer is a floating gate.  
     
     
         11 . A non-volatile memory cell comprising: 
 a semiconductor substrate;    a tunnel oxide formed over the semiconductor substrate;    a floating gate formed over the tunnel oxide comprising a plurality of charge, a depletion region and an accumulation region, wherein the accumulation region stores a greater concentration of charge than the depletion region;    an insulating layer formed on the floating gate, wherein the insulating layer is in physical contact with the accumulation region; and    a control gate formed over the insulating layer.    
     
     
         12 . The non-volatile memory cell of  claim 11 , wherein the floating gate is a bilayer, wherein a first layer is closest to the tunnel oxide and comprises silicon and a second layer is over the first layer, in physical contact with the insulating layer and comprises silicon and germanium.  
     
     
         13 . The non-volatile memory cell of  claim 12 , wherein the first layer is polysilicon and the second layer is silicon germanium.  
     
     
         14 . The non-volatile memory cell of  claim 12 , wherein the first layer is a material with a higher bandgap than the second material.  
     
     
         15 . The non-volatile memory cell of  claim 11 , wherein the greater concentration of charge is at least a majority of charge.  
     
     
         16 . The non-volatile memory cell of  claim 15 , wherein the depletion region stores substantially no charge.  
     
     
         17 . The non-volatile memory cell of  claim 11 , wherein the depletion region comprises a first dopant concentration and the accumulation region comprises a second dopant concentration, wherein the second dopant concentration is greater than the first dopant concentration.  
     
     
         18 . The non-volatile memory cell of  claim 11 , wherein the insulating layer is an oxide-nitride-oxide stack.  
     
     
         19 . A semiconductor device comprising: 
 a substrate;    a first insulating layer over the substrate;    a second insulating layer over the substrate;    a conductive layer formed over the second insulating layer; and    a charge storage layer between the first insulating layer and the second insulating layer comprising: 
 a first charge storage layer consisting of silicon; and  
 a second charge storage layer over the first charge storage layer consisting of silicon and germanium, wherein the second charge storage layer and the second insulating layer form an interface.  
   
     
     
         20 . The semiconductor device of  claim 19 , wherein the first charge storage layer is polysilicon.  
     
     
         21 . The semiconductor device of  claim 19 , wherein the charge storage layer stores a plurality of charge and a majority of the plurality of charge is stored at the interface.  
     
     
         22 . A method of forming a semiconductor device comprising: 
 providing a semiconductor device;    forming a first insulating layer over the semiconductor device;    forming a charge storage layer over the first insulating layer, wherein the charge storage layer stores a plurality of charge;    forming a second insulating layer on the charge storage layer, wherein the charge storage layer and the second insulating layer form an interface and at least a majority of the charge is stored substantially at the interface; and    forming a conductive layer over the second insulating layer.