Process for bonding and electrically connecting microsystems integrated in several distinct substrates

Abstract

A process for bonding two distinct substrates that integrate microsystems, including the steps of forming micro-integrated devices in at least one of two substrates using micro-electronic processing techniques and bonding the substrates. Bonding is performed by forming on a first substrate bonding regions of deformable material and pressing the substrates one against another so as to deform the bonding regions and to cause them to react chemically with the second substrate. The bonding regions are preferably formed by a thick layer of a material chosen from among aluminum, copper and nickel, covered by a thin layer of a material chosen from between palladium and platinum. Spacing regions ensure exact spacing between the two wafers.

1 . A process for bonding two distinct substrates integrating electronic and/or micro-electromechanical devices, comprising the steps of: 
 forming micro-integrated devices in at least one of two substrates, using micro-electronic processing techniques; and    bonding said substrates by: 
 forming, on a first of said substrates, bonding structures of deformable material; and by  
 pressing said substrates against each other so as to deform said bonding structures and cause said bonding structures to react chemically with a second substrate.  
   
     
     
         2 . The process according to  claim 1 , wherein said bonding structures comprise a stack of layers including a soft layer and a bonding layer.  
     
     
         3 . The process according to  claim 2 , further comprising a diffusion barrier layer between said soft layer and said bonding layer.  
     
     
         4 . The process according to  claim 2  wherein said soft layer is of a material chosen from among aluminum, aluminum and copper alloy, copper, and nickel, and said bonding layer is of a material chosen from between palladium and platinum.  
     
     
         5 . The process according to  claim 3 , wherein said diffusion barrier layer is of a material chosen from between chromium and titanium.  
     
     
         6 . The process according to  claim 1 , further comprising the step of forming spacing regions having a first depth, said bonding structure comprising bonding regions having a second depth greater than said first depth, wherein said pressing step comprises bringing said second substrate in abutment against said spacing regions.  
     
     
         7 . The process according to  claim 6 , wherein said step of forming bonding structures comprises: 
 depositing and defining a spacing layer on top of said first substrate to form said spacing regions;    depositing a sacrificial layer on top of said first substrate and said spacing regions;    selectively removing said sacrificial layer in areas to be bonded;    forming a stack of layers including a soft layer and a bonding layer;    defining said stack of layers to form said bonding regions ( 32 ) in said areas to be bonded; and    removing said sacrificial layer.    
     
     
         8 . An integrated device comprising: 
 first and second substrates, distinct from each other; and    bonding structures arranged between said first and second substrates, wherein said bonding structures include including portions of deformed material and portions of material derived from the reaction between said structures and said second substrate.    
     
     
         9 . The device according to  claim 8 , wherein said structures comprise a stack of layers including a soft layer and a bonding layer.  
     
     
         10 . The device according to  claim 9 , further comprising a diffusion barrier layer between said soft layer and said bonding layer.  
     
     
         11 . The device according to  claim 9  wherein said soft layer is of a material chosen from among aluminum, aluminum and copper alloy, copper, and nickel, and said bonding layer is of a material chosen from between palladium and platinum.  
     
     
         12 . The device according to  claim 10 , wherein said diffusion barrier layer is of a material chosen from between chromium and titanium.  
     
     
         13 . The device according to  claim 8 , further comprising spacing regions having smaller deformability than said portions of deformed material.  
     
     
         14 . The device according to  claim 13 , wherein said spacing regions surround at a distance said bonding structures.  
     
     
         15 . The device according to  claim 13  wherein said spacing regions are of insulating material.  
     
     
         16 . The device according to any of claims  13  wherein said spacing regions are of silicon dioxide.  
     
     
         17 . A device, comprising: 
 a first semiconductor substrate; and    a structure formed on a first surface of the substrate, configured to deform under a selected pressure and temperature, less than a pressure and temperature required to deform the substrate and further configured to bond with a first surface of a second substrate.    
     
     
         18 . The device of  claim 17  wherein the structure comprises a soft layer configured to deform and a bonding layer configured to bond with the second substrate.  
     
     
         19 . The device of  claim 18 , further comprising a diffusion barrier layer between the soft layer and the bonding layer.  
     
     
         20 . A method, comprising: 
 forming a layer on a first surface of a semiconductor substrate; and    defining, in the layer, a bonding structure configured to deform under a selected pressure and temperature, less than a pressure and temperature required to deform the substrate.    
     
     
         21 . The method of  claim 20  wherein the forming step includes forming, as a first part of the layer, a deformable layer, and forming, as a second part of the layer, a bondable layer.  
     
     
         22 . The method of  claim 21 , further comprising forming a diffusion barrier between the deformable layer and the bondable layer.  
     
     
         23 . The method of  claim 20 , further comprising forming, on the first surface of the semiconductor substrate, a spacing structure having a thickness less than the thickness of the layer.  
     
     
         24 . The method of  claim 23  wherein the spacing structure is one of a plurality of spacing structures formed on the first surface of the semiconductor layer.  
     
     
         25 . The method of  claim 20  wherein the semiconductor substrate is a first substrate, and further comprising: 
 positioning a second semiconductor substrate above the first surface of the first substrate; and  
 bonding the second substrate to the first substrate by biasing the first and second substrates together with the selected pressure and temperature, causing, thereby, the bonding structure to deform and bond with a first surface of the second substrate.