US2003109127A1PendingUtilityA1

Semiconductor device and method for fabricating the same

Assignee: MATSUSHITA ELECTRIC INDUSTRIAL CO LTDPriority: Oct 13, 2000Filed: Jan 24, 2003Published: Jun 12, 2003
Est. expiryOct 13, 2020(expired)· nominal 20-yr term from priority
H10W 20/072H10W 20/063H10W 20/46H10W 20/0633H10W 20/0693H10W 20/069
39
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

After a conductive film and a lower interlayer insulating film are formed successively on a semiconductor substrate, a lower plug connected to the conductive film is formed in the lower interlayer insulating film. Then, etching is performed sequentially with respect to the lower interlayer insulating film and the conductive film by using a mask pattern and the lower plug as a mask, thereby forming a lower-layer wire composed of the conductive film and connected to the lower plug. Thereafter, an upper interlayer insulating film is formed such that air gaps are formed in the wire-to-wire spaces of the lower-layer wire. Subsequently, an upper plug connected to the lower plug is formed in the upper interlayer insulating film. After that, an upper-layer wire is formed on the upper interlayer insulating film to be connected to the upper plug.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
         1 . A semiconductor device comprising: 
 a lower-layer wire formed on a semiconductor substrate and having an air gap in a wire-to-wire space;    an upper-layer wire formed on the lower-layer wire with an interlayer insulating film interposed therebetween; and    a plug connecting the lower-layer wire and the upper-layer wire,    the plug having a lower plug formed on the lower-layer wire and an upper plug formed on the lower plug to be connected to the upper-layer wire.    
     
     
         2 . The semiconductor device of  claim 1 , wherein an area of an upper surface of the lower plug is larger than an area of a lower surface of the upper plug.  
     
     
         3 . The semiconductor device of  claim 1 , further comprising: 
 an adjacent plug connecting the lower-layer wire and the upper-layer wire and adjacent to the plug, the adjacent plug having a lower adjacent plug formed on the lower-layer wire to be adjacent to the lower plug and an upper adjacent plug formed on the lower adjacent plug to be adjacent to the upper plug.    
     
     
         4 . The semiconductor device of  claim 1 , wherein 
 the interlayer insulating film is composed of a lower interlayer insulating film deposited to cover an upper surface of the lower-layer wire and an upper interlayer insulating film deposited on the lower interlayer insulating film and    the upper interlayer insulating film has a first insulating film deposited such that the air gap is formed and a second insulating film deposited on the first insulating film.    
     
     
         5 . The semiconductor device of  claim 4 , wherein the upper interlayer insulating film further has a third insulating film deposited on the second insulating film and having a surface planarized.  
     
     
         6 . The semiconductor device of  claim 5 , wherein a major part of the upper plug is covered with the third insulating film.

Join the waitlist — get patent alerts

Track US2003109127A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.