Semiconductor device having capacitive element and manufacturing method thereof

Abstract

A dielectric layer for capacitive element is formed on a lower electrode. An interlayer insulating layer is formed on the lower electrode and the dielectric layer for capacitive element. A plug hole reaching the dielectric layer for capacitive element is formed in the interlayer insulating layer. Upper electrodes are formed to fill in the plug hole and positioned opposite to the lower electrode with the dielectric layer for capacitive element interposed. The dielectric layer for capacitive element is in contact with the upper surface of the lower electrode at a region directly below the plug hole and a region outside the sidewall of the plug hole. Thus, a semiconductor device having a capacitive element with a greater capacitance which prevents diffusion of metal atoms from the lower electrode as well as a manufacturing method thereof are provided.

What is claimed is:  
     
         1 . A semiconductor device having a capacitive element, comprising: 
 a lower electrode layer;    a dielectric layer for capacitive element formed on said lower electrode layer;    an insulating layer formed on said lower electrode layer and said dielectric layer for capacitive element and having a hole reaching said dielectric layer for capacitive element; and    an upper electrode layer filling in said hole and positioned opposite to said lower electrode layer with said dielectric layer for capacitive element interposed,    said dielectric layer for capacitive element being in contact with an upper surface of said lower electrode layer at a region directly below said hole and a region outside a side wall of said hole.    
     
     
         2 . The semiconductor device having the capacitive element according to  claim 1 , wherein said dielectric layer for capacitive element is in contact with a side wall of said lower electrode layer.  
     
     
         3 . The semiconductor device having the capacitive element according to  claim 1 , wherein said dielectric layer for capacitive element has a side wall substantially continuous to a side wall of said lower electrode layer.  
     
     
         4 . A semiconductor device having a capacitive element, comprising: 
 a first lower electrode portion;    an insulating layer formed on said first lower electrode portion and having a hole reaching said first lower electrode portion;    a second lower electrode portion having a cylindrical portion formed along a sidewall of said hole and electrically connected to said first lower electrode portion;    a dielectric layer for capacitive element formed on said second lower electrode portion; and    an upper electrode layer filling in said hole and positioned opposite to said second lower electrode portion with said dielectric layer for capacitive element interposed.    
     
     
         5 . The semiconductor device having the capacitive element according to  claim 4 , wherein said second lower electrode portion is not on an upper surface of said insulating layer.  
     
     
         6 . The semiconductor device having the capacitive element according to  claim 4 , wherein said second lower electrode portion has a portion extending on an upper surface of said insulating layer.  
     
     
         7 . The semiconductor device having the capacitive element according to  claim 4 , wherein said hole has a diameter greater than an area of an upper surface of said first lower electrode portion.  
     
     
         8 . The semiconductor device having the capacitive element according to  claim 4 , wherein a plurality of said holes are formed, each of said plurality of holes uniquely reaching said first lower electrode portion, said second lower electrode portion has a portion extending along each of side walls of said holes, and said upper electrode layer fills in each of said holes.  
     
     
         9 . A method of manufacturing a semiconductor device having a capacitive element, comprising the steps of: 
 forming a dielectric layer for capacitive element on a lower electrode layer;    forming an insulating layer to cover said lower electrode layer and said dielectric layer for capacitive element;    forming a hole reaching said dielectric layer for capacitive element in said insulating layer; and    forming an upper electrode layer to fill in said hole.    
     
     
         10 . The method of manufacturing the semiconductor device having the capacitive element according to  claim 9 , wherein said step of forming said dielectric layer for capacitive element on said lower electrode layer includes the step of forming said dielectric layer for capacitive element to cover an upper and side surfaces of said lower electrode layer after patterning said lower electrode layer.  
     
     
         11 . The method of manufacturing the semiconductor device having the capacitive element according to  claim 9 , wherein said step of forming said dielectric layer for capacitive element on said lower electrode layer includes the step of forming said dielectric layer for capacitive element on a conductive layer later to be said lower electrode layer and then patterning said conductive layer and said dielectric layer for capacitive element.  
     
     
         12 . A method of manufacturing a semiconductor device having a capacitive element, comprising the steps of: 
 forming a first lower electrode portion;    forming an insulating layer on said first lower electrode portion;    forming a hole reaching said first lower electrode portion in said insulating layer;    forming a second lower electrode portion having a portion extending along a side wall of said hole and electrically connected to said first lower electrode portion;    forming a dielectric layer for capacitive element on said second lower electrode portion; and    forming an upper electrode layer filling in said hole and positioned opposite to said second lower electrode portion with said dielectric layer for capacitive element interposed.    
     
     
         13 . The method of manufacturing the semiconductor device having the capacitive element according to  claim 12 , wherein said step of forming said second lower electrode portion includes the step of forming a conductive layer, later to be said second lower electrode portion, to cover an inner surface of said hole and an upper surface of said insulating layer and then patterning and leaving it only in said hole.  
     
     
         14 . The method of manufacturing the semiconductor device having the capacitive element according to  claim 12 , wherein said step of forming said second lower electrode portion includes the step of forming a conductive layer, later to be said second lower electrode portion, to cover an inner surface of said hole and an upper surface of said insulating layer and patterning it along with said dielectric layer for capacitive element formed on the conductive layer, later to be said second lower electrode portion, to leave them in said hole and on a part of the upper surface of said insulating layer.  
     
     
         15 . The method of manufacturing the semiconductor device having the capacitive element according to  claim 12 , wherein said hole is formed to have a diameter greater than an area of an upper surface of said first lower electrode portion.  
     
     
         16 . The method of manufacturing the semiconductor device having the capacitive element according to  claim 12 , wherein a plurality of said holes are formed, each uniquely reaching said first lower electrode portion, said second lower electrode portion has a portion extending along a side wall of said plurality of holes, and said upper electrode layer are formed to fill in each of said plurality of holes.