High performance multi-chip flip chip package

Abstract

A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of laminating material. A silicon die is attached inside a cavity formed in each lead frame. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of each die as well as the edges of the lead frame adjacent to each die.

What is claimed is:  
     
         1 . A multi-chip semiconductor package comprising: 
 a base layer;    a dielectric layer of laminating medium disposed over the base layer;    a lead frame layer disposed over the dielectric layer, the lead frame layer having a plurality of cavities;    a plurality of silicon dies attached inside the plurality of cavities, respectively, wherein each cavity is sized such that a surface of the silicon die attached therein and a surface of an edge of the lead frame layer adjacent to the silicon die form a substantially uniform plane; and    an array of solder balls including an inner array distributed across the uniform plane disposed on the surface of each silicon die, and an outer array disposed on the surface of the edges of the lead frame layer adjacent to each silicon die.    
     
     
         2 . The multi-chip semiconductor package of  claim 1  wherein the lead frame layer is made of electrically conductive material.  
     
     
         3 . The multi-chip semiconductor package of  claim 2  wherein the lead frame layer is physically divided into a plurality of electrically isolated sections.  
     
     
         4 . The multi-chip semiconductor package of  claim 3  wherein each of the plurality of cavities is formed inside each of the plurality of electrically isolated sections of the lead frame layer, respectively.  
     
     
         5 . The multi-chip semiconductor package of  claim 4  wherein the lead frame layer makes electrical contact with a substrate side of a silicon die attached therein.  
     
     
         6 . The multi-chip semiconductor package of  claim 5  wherein each of the plurality of silicon dies comprises a power MOSFET having a drain terminal, a source terminal, and a gate terminal.  
     
     
         7 . The multi-chip semiconductor package of  claim 6  wherein the drain terminal of each power MOSFET connects to its respective lead frame layer, the source terminal of the power MOSFET connects to a substantial number of the inner array of solder balls, and the gate terminal of the power MOSFET connects to one of the inner array of solder balls.  
     
     
         8 . The multi-chip semiconductor package of  claim 7  wherein the lead frame layer is etched into four electrically isolated lead frame sections each receiving a power MOSFET die.  
     
     
         9 . The multi-chip semiconductor package of  claim 2  wherein the lead frame layer and the outer array of solder balls are configured to act as a thermal via.  
     
     
         10 . The multi-chip semiconductor package of  claim 4  wherein the base layer comprises ceramic and the lead frame layer comprises copper.  
     
     
         11 . A multi-chip semiconductor package comprising: 
 a base layer;    a dielectric layer of laminating medium disposed over the base layer;    an electrically conductive lead frame layer disposed over the dielectric layer, the lead frame layer being physically divided into a plurality of electrically isolated lead frame sections, each section having a cavity;    a plurality of silicon dies each having its substrate attached inside and making electrical contact with a respective cavity; and    an inner array of solder balls distributed across an active surface of each of the plurality of silicon dies, and an outer array of solder balls disposed on a surface of cavity edges of the lead frame layers.    
     
     
         12 . The multi-chip semiconductor package of  claim 10  wherein the plurality of silicon dies comprises power MOSFETs, and wherein connection to a drain terminal of each power MOSFET is made via its respective lead frame layer, and connection to a source terminal and a gate terminal of each MOSFET is made via its respective plurality of inner array of solder balls.  
     
     
         13 . A method for packaging a plurality of silicon dies inside a single package comprising the steps of: 
 forming a multi-layer carrier having a base layer, a laminating dielectric middle layer and a conductive lead frame upper layer;    etching through the lead frame layer to form a plurality of electrically isolated lead frame sections;    stamping a cavity inside each of the plurality of electrically isolated lead frame sections;    attaching a first surface of a silicon die inside each cavity such that a second surface of the silicon die and a surface of the edges of the lead frame layer adjacent to the silicon die form a substantially uniform plane; and    disposing an array of solder balls across the substantially uniform plane with an outer array connecting to the lead frame layer and an inner array connecting to the second surface of the silicon die.    
     
     
         14 . The method of  claim 13  wherein the step of disposing an array of solder balls occurs prior to the attaching step and comprises a step of forming solder balls on the second surface of the silicon die, and a step of forming solder balls on the surface of the edges of the lead frame layer adjacent to the silicon die.