Self-aligned dual-floating gate memory cell .

Abstract

An integrated circuit that includes a first dual-floating gate memory cell having a first floating gate isolated from a second floating gate for storing at least one bit of datum, and a second dual-floating gate memory cell having a third floating gate isolated from a fourth floating gate for storing at least one bit of datum, wherein the first dual-floating gate memory cell and the second dual-floating gate memory cell share a control gate, wherein the second floating gate of the first dual-floating gate memory cell shares an oxide layer with the third floating gate of the second dual-floating gate memory cell, and wherein the oxide layer electrically insulates the second and third floating gates from the control gate.

What is claimed is:  
     
         1 . An integrated circuit, comprising: 
 a first dual-floating gate memory cell having a first floating gate isolated from a second floating gate for storing at least one bit of datum, and    a second dual-floating gate memory cell having a third floating gate isolated from a fourth floating gate for storing at least one bit of datum,    wherein the first dual-floating gate memory cell and the second dual-floating gate memory cell share a control gate,    wherein the second floating gate of the first dual-floating gate memory cell shares an oxide layer with the third floating gate of the second dual-floating gate memory cell, and    wherein the oxide layer electrically insulates the second and third floating gates from the control gate.    
     
     
         2 . The integrated circuit as claimed in  claim 1 , wherein one of the first, second, third and fourth floating gates has a vertical dimension greater than or equal to a horizontal dimension.  
     
     
         3 . The integrated circuit as claimed in  claim 1 , wherein all of the first, second, third and fourth floating gates have a vertical dimension greater or equal to than a horizontal dimension.  
     
     
         4 . The integrated circuit as claimed in  claim 1 , further comprising a first isolation oxide to isolate the first floating gate from the second floating gate.  
     
     
         5 . The integrated circuit as claimed in  claim 1 , further comprising a second isolation oxide to isolate the third floating gate from the fourth floating gate.  
     
     
         6 . A method for manufacturing a semiconductor device, comprising: 
 defining a substrate;    providing a dielectric layer over the substrate;    depositing a first layer of polysilicon over the dielectric layer;    providing a layer of nitride over the first layer of polysilicon;    forming a plurality of composite structures, each having a section of the first polysilicon layer and nitride layer;    forming a plurality of diffused regions in the substrate between the plurality of composite structures;    forming isolation oxides between the plurality of composite structures;    removing the sections of the nitride layer;    forming a plurality of spacers over the first polysilicon layer and contiguous with sidewalls of the isolation oxides;    etching the first polysilicon layer with the plurality of spacers acting as masks;    removing the plurality of spacers;    forming a layer of inter-gate dielectric over the etched first polysilicon layer; and    forming a second polysilicon layer over the inter-gate dielectric layer.    
     
     
         7 . The method as claimed in  claim 6 , wherein the step of forming a plurality of spacers includes forming a plurality of oxide spacers.  
     
     
         8 . The method as claimed in  claim 7 , further comprising a step of depositing a layer of oxide.  
     
     
         9 . The method as claimed in  claim 6 , wherein the step of forming a plurality of spacers includes forming a plurality of polysilicon spacers.  
     
     
         10 . The method as claimed in  claim 9 , further comprising a step of depositing a layer of polysilicon.  
     
     
         11 . The method as claimed in  claim 6 , wherein the step of forming isolation oxides between the plurality of composite structures includes a step of high-density plasma oxide deposition.  
     
     
         12 . The method as claimed in  claim 6 , further comprising a step of chemical-mechanical polishing of the isolation oxides.  
     
     
         13 . A method for manufacturing a semiconductor device, comprising: 
 defining a substrate;    forming a dielectric layer over the substrate;    depositing a first layer of polysilicon over the dielectric layer;    providing a layer of nitride over the first layer of polysilicon;    etching the layer of nitride and the first layer of polysilicon to form a plurality of composite structures, each having a section of the first polysilicon layer and nitride layer;    depositing a layer of oxide using high-density plasma deposition over and between the plurality of composite structures;    removing the nitride layer;    forming a plurality of spacers over the first polysilicon layer;    etching the first polysilicon layer with the plurality of spacers acting as masks;    removing the plurality of spacers;    forming an inter-gate dielectric layer over the etched first polysilicon layer; and    forming a second polysilicon layer over the inter-gate dielectric layer.    
     
     
         14 . The method as claimed in  claim 13 , wherein the spacers are oxide spacers.  
     
     
         15 . The method as claimed in  claim 13 , wherein the spacers are polysilicon spacers.  
     
     
         16 . The method as claimed in  claim 13 , further comprising a step of chemical-mechanical polishing of the oxide layer.