Super self -aligned heterojunction biplar transistor and its manufacturing method

Abstract

A super self-aligned heterojunction bipolar semiconductor device and its manufacturing method are disclosed. The present invention provides a super self-aligned heterojunction bipolar transistor that may maintain the operational stability and the uniformity of a device, facilitate the manufacturing process, and reduce manufacturing time by employing a highly concentrated thick polysilicon film; and its manufacturing method. Also, the present invention provides a super self-aligned heterojunction bipolar transistor that may reduce noise by making the base resistance reduced by a highly concentrated thick polysilicon film, and may minimize the parasitic capacitance between a collector and a base and between a base and an emitter, and the parasitic resistance of a base, so as to realize high-speed operation of a device; and its manufacturing method.

What is claimed is:  
     
         1 . A method of manufacturing a heterojunction bipolar transistor comprising: 
 a) forming a sub-collector by ion-implanting dopant into a portion of a semiconductor substrate and diffusing it;    b) forming a field insulating film by forming a collector layer on the entire surface of the semiconductor substrate and oxidizing a region except at an active collector region and a collector sinker by a localized oxidation of silicon (LOCOS) method;    c) ion-implanting dopant into the collector sinker using a photo mask; heat-treating; diffusing; and removing the collector sinker to have a predetermined thickness; and forming a sinker protection film;    d) forming a base electrode by evaporating a thermal oxidation film, a base electrode, and a base electrode protection film on the entire surface of the field insulating film, the active collector region, and the sinker protection film;    e) exposing the active collector region and the sinker protection film by etching the base electrode, the base electrode protection film and the thermal oxidation film in a predetermined pattern;    f) forming an intrinsic collector by ion-implanting dopant into the active collector region and heat-treating;    g) forming a SiGe base layer on the entire surface of the protection film, the intrinsic collector and the sinker protection film;    h) forming a masking film by evaporating a buffer protection film on the entire surface of the SiGe base layer and dry-etching the buffer protection film;    i) separating the base and the emitter by removing the masking film by wet-etching and forming a first sidewall film and a second sidewall film;    j) forming an emitter electrode by removing the second sidewall film and the first insulating film by etching and evaporating polysilicon on the base layer;    k) removing the base electrode protection film by dry-etching so as to expose the base electrode; and evaporating a silicon oxide film so as to protect the emitter electrode from the damage by dry-etching when the emitter sidewall film is formed;    l) forming an emitter sidewall film by evaporating a silicon nitride film or a silicon oxide film and dry-etching in a predetermined pattern;    m) forming an ohmic electrode only on the emitter electrode and the base electrode by exposing the emitter electrode and the base electrode by wet-etching, heat-treating, sputtering titanium (Ti) and titanium nitride (TiN) and wet-etching;    n) forming an emitter contact window, a base contact window and a collector contact window by evaporating silicon oxide or silicon nitride on the entire surface of the semiconductor substrate whereon the ohmic electrode is formed to form an insulating film and patterning the insulating film and the sinker protection film using a photo mask; and    o) forming a base terminal, an emitter terminal and a collector terminal by cleaning the surface of the semiconductor substrate according to the standard cleaning process, forming barrier metal by sputtering titanium (Ti) and titanium nitride (TiN), evaporating a conductive metal, heat-treating and patterning.    
     
     
         2 . The method according to  claim 1 , wherein the sub-collector is formed by ion-implanting dopant with a concentration of from about 5×10 19  cm −3  to about 1×10 20  cm −3  into a portion of the semiconductor substrate having a resistivity larger than about 50/Ωcm, and diffusing the dopant.  
     
     
         3 . The method according to  claim 1 , wherein the field insulating film is formed by oxidizing the collector layer formed on the entire surface of the semiconductor substrate except the active collector region and the collector sinker to a thickness of about 500 nm to about 1200 nm by a localized oxidation of silicon process (LOCOS) method.  
     
     
         4 . The method according to  claim 1 , wherein the sinker protection film is formed by ion-implanting n+ type dopant with a concentration from about 5×10 19  cm −3  to about 1×10 20  cm −3  into the collector sinker, heat-treating and diffusing the dopant, and removing an upper part of the collector sinker using photoresist.  
     
     
         5 . The method according to  claim 1 , wherein the base electrode is formed by forming a thermal oxidation film comprising polysilicon with a thickness of about 20 nm-100 nm on the entire surface of the field insulating film, the active collector region and the sinker protection film at a temperature of between about 900-1000° C.; evaporating the base electrode comprising polysilicon with a thickness of about 200 nm to about 600 nm by doping p+ type dopant with a concentration higher than about 1×10 19  cm −3  into the entire surface of the thermal oxidation film by in-situ method; evaporating the base electrode protection film comprising silicon nitride or silicon oxide with a thickness of about 200 nm to about 600 nm for protecting the base electrode; and removing the base electrode and the base electrode protection film by dry-etching using a photo mask.  
     
     
         6 . The method according to  claim 1 , wherein the exposing step is performed by wet-etching the thermal oxidation film with HF, NH 4 F or their mixture and exposing the active collector region and the sinker protection film.  
     
     
         7 . The method according to  claim 1 , wherein the collector is formed by ion-implanting n+ type dopant with a concentration of from about 1×10 16  cm −3  to about 5×10 18  cm 3  into the active collector region and heat-treating.  
     
     
         8 . The method according to  claim 1 , wherein the base layer is formed by forming silicon layer on the entire surface of the base electrode protection film, the intrinsic collector, and the sinker protection film, and growing an undoped SiGe film, SiGe doped with p+ type dopant, and an undoped silicon film in order.  
     
     
         9 . The method according to  claim 8 , wherein the SiGe base layer has a thickness of about 50 nm to about 100 nm.  
     
     
         10 . The method according to  claim 1 , wherein the SiGe base layer has a thickness of about 50 nm to about 100 nm.  
     
     
         11 . The method according to  claim 1 , wherein the concentration of Ge ranges from about 1% to about 20% and the doping concentration of dopant ranges from about 5×10 18  cm 3  to about 3×10 20  cm −3 .  
     
     
         12 . The method according to  claim 8 , wherein the concentration of Ge ranges from about 1% to about 20% and the doping concentration of dopant ranges from about 5×10 18  cm −3  to about 3×10 20  cm −3 .  
     
     
         13 . The method according to  claim 1 , wherein the masking film is formed by evaporating the buffer protection film on the entire surface of the SiGe base layer by means of a low pressure chemical vapor deposition (LPCVD) method; and removing the buffer protection film by dry-etching so that the buffer protection film reaches an upper surface of the base electrode.  
     
     
         14 . The method according to  claim 1 , wherein the base and the emitter are separated by removing an exposed portion of the base layer by dry-etching; removing the masking film by wet-etching; and evaporating the first sidewall film and the second sidewall film on the base layer using a low pressure vapor deposition (LPCVD) method.  
     
     
         15 . The method according to  claim 14 , wherein the first sidewall film comprises a silicon oxide film or a silicon nitride film with a thickness of about 50 nm to about 300 nm.  
     
     
         16 . The method according to  claim 14 , wherein the second sidewall film comprises a silicon oxide film or a silicon nitride film with a the thickness of the second sidewall film ranges from about 200 nm to about 800 nm.  
     
     
         17 . The method according to  claim 1 , wherein the emitter electrode is formed by removing the second sidewall film by dry-etching; removing the first sidewall by wet-etching; and evaporating n+ type polysilicon on the base layer.  
     
     
         18 . The method according to  claim 16 , wherein the emitter electrode is formed by diffusing n+ type dopant into the base layer to form a junction between the base and the emitter, and patterning the emitter electrode using a photo mask.  
     
     
         19 . The method according to  claim 1 , wherein the emitter sidewall film is formed by removing the base electrode protection film by dry-etching; evaporating a silicon nitride film or a silicon oxide film with a thickness of about 200 nm to about 1000 nm on the surface of the emitter electrode and the base electrode; and dry-etching in a predetermined pattern.  
     
     
         20 . The method according to  claim 1 , wherein the ohmic electrode is formed by exposing the emitter electrode and the base electrode by wet-etching; sputtering titanium (Ti) and titanium nitride (TiN) on the surface of the semiconductor substrate; heat-treating; and forming the ohmic electrode only on the emitter electrode and the base electrode by wet-etching.  
     
     
         21 . The method according to  claim 20 , wherein the ohmic electrode is formed to have a thickness of about 40 nm to about 60 nm.  
     
     
         22 . The method according to  claim 1 , wherein the ohmic electrode has a thickness of about 40 nm to about 60 nm.  
     
     
         23 . The method according to  claim 1 , wherein the base contact window, the emitter contact window and the collector contact window are formed by forming the insulating film through evaporating silicon oxide or silicon nitride on the surface of the semiconductor substrate whereon the ohmic electrode is formed; and patterning the insulating film and the sinker protection film using a photo mask.  
     
     
         24 . The method according to  claim 1 , wherein the base terminal, the emitter terminal and the collector terminal are formed by cleaning the surface of the semiconductor substrate by a standard cleaning process; forming barrier metal by sputtering titanium (Ti) and titanium nitride (TiN), evaporating a metal selected from the group consisting of aluminum (Al), aluminum-silicon (Al—Si), copper (Cu) and gold (Au), heat-treating; and patterning.  
     
     
         25 . A super self-aligned heterojunction bipolar transistor comprising: 
 a) a sub-collector formed by ion-implanting dopant into a portion of a semiconductor substrate and diffusing it;    b) a field insulating film formed by forming a collector layer on the entire surface of the semiconductor substrate, and oxidizing a region except an active collector region and an collector sinker, wherein dopant is ion-implanted into the collector sinker, and wherein the collector layer is heat-treated and the ions are diffused in the collector sinker;    c) a sinker protection film formed by removing the collector sinker to a predetermined thickness and forming a film on the collector sinker;    d) a thermal oxidation film formed on the entire surface of the field insulating film, the active collector region and the sinker-protection film;    e) a base electrode formed on the entire surface of the thermal oxidation film with a predetermined thickness by in-situ method; wherein a base electrode protection film is formed on the base electrode with a predetermined thickness so as to protect the base electrode;    f) an intrinsic collector formed by dry-etching the base electrode and the base electrode protection film in a predetermined pattern; wet-etching the thermal oxidation film so as to expose the active collector region and the sinker protection film; ion-implanting dopant into the active collector region; and heat-treating;    g) a SiGe base layer formed on the entire surface of the base electrode protection film, the intrinsic collector and the sinker protection film;    h) a first sidewall film and a second sidewall film formed by removing a masking film by wet-etching, wherein the masking film is formed by dry-etching a buffer protection film formed on the entire surface of the SiGe base layer; and evaporating a silicon oxide film or a silicon nitride film to a predetermined thickness;    i) an emitter electrode formed by removing the second sidewall film and the first sidewall film respectively by etching; evaporating polysilicon on the base layer; heat-treating; and patterning;    j) an emitter sidewall film formed by exposing the base electrode by dry-etching; evaporating a silicon nitride film or a silicon oxide film on the base electrode; heat-treating; and wet-etching;    k) an ohmic electrode formed on the emitter electrode and an exposed portion of the base electrode by sputtering titanium (Ti) and titanium nitride (TiN) in order on the emitter electrode and the base electrode, heat-treating, and wet-etching;    l) an insulating film formed by evaporating silicon oxide or silicon nitride on the entire surface of the semiconductor substrate;    m) a barrier metal formed by forming an emitter contact window, a base contact window and a collector contact window by patterning the insulating film and the sinker protection film using a photo mask; cleaning the surface of the semiconductor substrate; and sputtering titanium (Ti) and titanium nitride (TiN); and    n) a base terminal, an emitter terminal, and a collector terminal provided by evaporating a conductive metal on the barrier metal, heat-treating and patterning.    
     
     
         26 . The super self-aligned heterojunction bipolar transistor according to  claim 25 , wherein the sub-collector is formed by ion-implanting dopant with a concentration of about 5×10 19  cm −3  into a portion of a semiconductor substrate and diffusing the dopant.  
     
     
         27 . The super self-aligned heterojunction bipolar transistor according to  claim 25 , wherein the field insulating film is formed by performing a localized oxidation of silicon process (LOCOS) to oxidize the collector layer except the active collector region and the collector sinker.  
     
     
         28 . The super self-aligned heterojunction bipolar transistor according to  claim 27 , wherein the collector layer is formed with a thickness of about 500 nm to about 1200 nm on the semiconductor substrate by a thermal oxidation method.  
     
     
         29 . The super self-aligned heterojunction bipolar transistor according to  claim 25 , wherein the collector layer is formed with a thickness of about 500 nm to about 1200 nm on the semiconductor substrate by a thermal oxidation method.  
     
     
         30 . The super self-aligned heterojunction bipolar transistor according to  claim 25 , wherein the sinker protection film is formed by ion-implanting dopant with a concentration of about 5×10 19  cm −3  to about 1×10 20  cm −3  into the collector sinker, heat-treating, diffusing and removing a part of the upper surface of the collector sinker using a photo resist.  
     
     
         31 . The super self-aligned heterojunction bipolar transistor according to  claim 25 , wherein the thermal oxidation film is a silicon oxide film formed with a thickness of about 20 nm to about 100 nm on the entire surface of the active collector region and the sinker protection film.  
     
     
         32 . The super self-aligned heterojunction bipolar transistor according to  claim 31 , wherein the thermal oxidation film is a silicon oxide film, which is formed at a temperature of between about 900-1000° C.  
     
     
         33 . The super self-aligned heterojunction bipolar transistor according to  claim 25 , wherein the thermal oxidation film is a silicon oxide film formed at a temperature of between about 900-1000° C.  
     
     
         34 . The super self-aligned heterojunction bipolar transistor according to  claim 25 , wherein the base electrode is a polysilicon film with a thickness of about 200 nm to about 600 nm, which is formed by doping dopant having a concentration higher than about 1×10 19  cm −3  into the entire surface of the thermal oxidation film by an in-situ process.  
     
     
         35 . The super self-aligned heterojunction bipolar transistor according to  claim 25 , wherein the base electrode protection film is a silicon nitride film or a silicon oxide film evaporated on the base electrode with a thickness of about 200 nm to about 600 nm.  
     
     
         36 . The super self-aligned heterojunction bipolar transistor according to  claim 25 , wherein the intrinsic collector is formed by exposing the base electrode and the base electrode protection film by dry-etching; wet-etching the thermal oxidation film using HF, NH 4 F or a mixture thereof; ion-implanting dopant with a concentration of about 1×10 16  cm −3  to about 5×10 18  cm −3  into the active collector region; and heat-treating.  
     
     
         37 . The super self-aligned heterojunction bipolar transistor according to  claim 25 , wherein the SiGe base layer is formed by growing in order a silicon film formed on the entire surface of the base electrode protection film, the intrinsic collector, and the sinker protection film, an undoped SiGe film, a SiGe film doped with p+ type dopant, and an undoped silicon film.  
     
     
         38 . The super self-aligned heterojunction bipolar transistor according to  claim 37 , wherein the silicon film formed on the entire surface of the intrinsic collector and the sinker protection film has a thickness of about 10 nm to about 60 nm.  
     
     
         39 . The super self-aligned heterojunction bipolar transistor according to  claim 37 , wherein the SiGe base layer has a thickness of about 50 nm to about 100 nm.  
     
     
         40 . The super self-aligned heterojunction bipolar transistor according to  claim 37 , wherein the concentration of the Ge that forms the SiGe base layer ranges from about 1% to about 20%, and the doping concentration of the ion-implanted dopant ranges from about 5×10 18  cm −3  to about 3×10 20  cm −3 .  
     
     
         41 . The super self-aligned heterojunction bipolar transistor according to  claim 25 , wherein the silicon film formed on the entire surface of the intrinsic collector and the sinker protection film has a thickness of about 10 nm to about 60 nm.  
     
     
         42 . The super self-aligned heterojunction bipolar transistor according to  claim 25 , wherein the SiGe base layer has a thickness of about 50 nm to about 100 nm.  
     
     
         43 . The super self-aligned heterojunction bipolar transistor according to  claim 25 , wherein the concentration of the Ge that forms the SiGe base layer ranges from about 1% to about 20% and the doping concentration of the ion-implanted dopant is ranges from about 5×10 18  cm −3  to about 3×10 20  cm −3 .  
     
     
         44 . The super self-aligned heterojunction bipolar transistor according to  claim 25 , wherein the buffer protection film is a silicon oxide film formed on the entire surface of the SiGe base layer by a low pressure chemical vapor deposition (LPCVD) method.  
     
     
         45 . The super self-aligned heterojunction bipolar transistor according to  claim 25 , wherein the buffer protection film is a silicon nitride film formed on the entire surface of the SiGe base layer by a low pressure chemical vapor deposition (LPCVD) method.  
     
     
         46 . The super self-aligned heterojunction bipolar transistor according to  claim 25 , wherein the masking film is a silicon oxide film formed by dry-etching the buffer protection film so that the buffer protection film reaches the upper surface of the base electrode.  
     
     
         47 . The super self-aligned heterojunction bipolar transistor according to  claim 25 , wherein the first sidewall film is a silicon oxide film or a silicon nitride film which is formed on the base layer, and wherein the base layer is exposed by removing the masking film by wet-etching.  
     
     
         48 . The super self-aligned heterojunction bipolar transistor according to  claim 47 , wherein the first sidewall film is a silicon oxide film or a silicon nitride film with a thickness of about 50 nm to about 300 nm, and wherein the first sidewall film is formed on an exposed portion of the base layer by a low pressure chemical vapor deposition (LPCVD) method.  
     
     
         49 . The super self-aligned heterojunction bipolar transistor according to  claim 25 , wherein the first sidewall film is a silicon oxide film or a silicon nitride film with a thickness of about 50 nm to about 300 nm, and wherein the is formed on an exposed portion of the base layer by a low pressure chemical vapor deposition (LPCVD) method.  
     
     
         50 . The super self-aligned heterojunction bipolar transistor according to  claim 25 , wherein the second sidewall film is a silicon oxide film or a silicon nitride film with a thickness of about 200 nm to about 800 nm, wherein the second sidewall film is formed on the first sidewall film by a low pressure chemical vapor deposition (LPCVD) method.  
     
     
         51 . The super self-aligned heterojunction bipolar transistor according to  claim 25 , wherein the emitter electrode is a polysilicon film which is formed by removing the second sidewall film by dry-etching; removing the first sidewall film by wet-etching; and evaporating on the base layer.  
     
     
         52 . The super self-aligned heterojunction bipolar transistor according to  claim 51 , wherein the emitter electrode is a polysilicon film formed by removing the second sidewall film by dry-etching; removing the first sidewall film by wet-etching; and evaporating on an exposed portion of the base layer.  
     
     
         53 . The super self-aligned heterojunction bipolar transistor according to  claim 51 , wherein the emitter electrode is formed by diffusing dopant contained in the polysilicon into the base layer; and patterning using a photo mask.  
     
     
         54 . The super self-aligned heterojunction bipolar transistor according to  claim 25 , wherein the emitter electrode is a polysilicon film formed by removing the second sidewall film by dry-etching; removing the first sidewall film by wet-etching; and evaporating on an exposed portion of the base layer.  
     
     
         55 . The super self-aligned heterojunction bipolar transistor according to  claim 25 , wherein the emitter electrode is formed by diffusing dopant contained in the polysilicon into the base layer; and patterning using a photo mask.  
     
     
         56 . The super self-aligned heterojunction bipolar transistor according to  claim 25 , wherein the emitter sidewall film is a silicon nitride film or a silicon oxide film formed by removing the base electrode protection film by dry-etching; evaporating on the emitter electrode and the base electrode with a thickness of about 200 nm to about 1000 nm; and removing in a predetermined pattern by wet-etching.  
     
     
         57 . The super self-aligned heterojunction bipolar transistor according to  claim 25 , wherein the ohmic electrode comprises titanium silicide (TiSi 2 ) wherein the ohmic electrode is formed by sputtering titanium (Ti) and titanium nitride (TiN) and heat-treating on the emitter electrode and the base electrode, and wherein the emitter electrode and the based electrode are exposed by wet-etching.  
     
     
         58 . The super self-aligned heterojunction bipolar transistor according to  claim 57 , wherein the ohmic electrode is a titanium silicide (TiSi 2 ) with a thickness of about 40 nm to about 60 nm.  
     
     
         59 . The super self-aligned heterojunction bipolar transistor according to  claim 25 , wherein the ohmic electrode comprises a titanium silicide (TiSi 2 ), and wherein the ohmic electrode has a thickness of about 40 nm to about 60 nm.  
     
     
         60 . The super self-aligned heterojunction bipolar transistor according to  claim 25 , wherein the insulating film is a silicon oxide or a silicon nitride evaporated on the semiconductor substrate whereon the ohmic electrode is formed.  
     
     
         61 . The super self-aligned heterojunction bipolar transistor according to  claim 25 , wherein the barrier metal is formed by patterning the insulating film and the sinker protection film to form an emitter contact window, a base contact window, and a collector contact window; cleaning the surface of the semiconductor substrate according to the standard cleaning process; and sputtering titanium (Ti) and titanium nitride (TiN).  
     
     
         62 . The super self-aligned heterojunction bipolar transistor according to  claim 25 , wherein the conductive metal evaporated on the barrier metal is heat-treated and patterned so as to form a base terminal, an emitter terminal, and a collector terminal.  
     
     
         63 . The super self-aligned heterojunction bipolar transistor according to  claim 62 , wherein the conductive metal evaporated on the barrier metal is selected from the group consisting of aluminium (Al), aluminium-silicon (Al—Si), copper (Cu) and gold (Au).  
     
     
         64 . The super self-aligned heterojunction bipolar transistor according to  claim 25 , wherein the conductive metal evaporated on the barrier metal is selected from the group consisting of aluminium (Al), aluminium-silicon (Al—Si), copper (Cu) and gold (Au).