Semiconductor device

Abstract

There is disclosed a semiconductor device comprising a copper interconnect layer 7 where a copper film is buried in a concave in an insulating film 3 via a barrier metal film, wherein the copper interconnect layer 7 has a line/space ratio of 4.5 or less and an interconnect occupancy of 10 to 60%. It can effectively prevent dishing and erosion, as well as increase and dispersion in an interconnect resistance when forming damascene copper interconnects.

What is claimed is:  
     
         1 . A semiconductor device comprising an interconnect layer where copper interconnects are buried in a concave in an insulating film via a barrier metal film, wherein the interconnect occupancy of the interconnect layer is 10 to 60%.  
     
     
         2 . A semiconductor device comprising an interconnect layer where copper interconnects are buried in a concave in an insulating film via a barrier metal film, wherein the interconnect layer comprises an interconnect area in which a plurality of copper interconnects are extended over 100 μm or more in one direction and an average line/space ratio in the copper interconnects in the interconnect area is 4.5 or less.  
     
     
         3 . The semiconductor device as claimed in  claim 2  where a line/space ratio of copper interconnects in the interconnect area is up to 5.  
     
     
         4 . The semiconductor device as claimed in  claim 2  where the interconnect occupancy of the interconnect layer is 10 to 60%.  
     
     
         5 . The semiconductor device as claimed in  claim 1  where the copper interconnects have a thickness of 350 nm or less.  
     
     
         6 . The semiconductor device as claimed in  claim 2  where the copper interconnects have a thickness of 350 nm or less.  
     
     
         7 . The semiconductor device as claimed in  claim 1  where the interconnect layer is the lowest interconnect layer in the plurality of interconnect layers deposited on the semiconductor substrate.  
     
     
         8 . The semiconductor device as claimed in  claim 2  where the interconnect layer is the lowest interconnect layer in the plurality of interconnect layers deposited on the semiconductor substrate.  
     
     
         9 . The semiconductor device as claimed in  claim 1  where the upper surfaces of the copper interconnects are leveled by chemical mechanical polishing.  
     
     
         10 . The semiconductor device as claimed in  claim 2  where the upper surfaces of the copper interconnects are leveled by chemical mechanical polishing.  
     
     
         11 . The semiconductor device as claimed in  claim 1  where the interconnect layer further comprises a probe pad area and an interconnect-occupancy in the probe pad area is 70 to 90%.  
     
     
         12 . The semiconductor device as claimed in  claim 2  where the interconnect layer further comprises a probe pad area and an interconnect occupancy in the probe pad area is 70 to 90%.  
     
     
         13 . A process for manufacturing a semiconductor device comprising the steps of depositing an insulating film on a semiconductor substrate surface including a device-forming area and then forming a concave in the insulating film within the device-forming area; depositing a barrier metal film in the concave and forming a copper film to fill the concave; and removing the copper film formed in the area outside the concave by chemical mechanical polishing to form copper interconnects, wherein the interconnect occupancy of the copper interconnects in the device-forming area is 10 to 60%.  
     
     
         14 . A process for manufacturing a semiconductor device comprising the steps of depositing an insulating film on a semiconductor substrate surface including a device-forming area and then forming a plurality of concaves extending over 100 μm or more in one direction within the device-forming area; depositing a barrier metal film in the concave and forming a copper film to fill the concave; and removing the copper film formed in the area outside the concave by chemical mechanical polishing to form a plurality of copper interconnects, wherein an average line/space ratio in the interconnect area is 4.5 or less.  
     
     
         15 . The process for manufacturing a semiconductor device as claimed in  claim 14  where a line/space ratio of copper interconnects in the interconnect area is up to 5.  
     
     
         16 . The process for manufacturing a semiconductor device as claimed in  claim 13  where the interconnect occupancy of the copper interconnects in the device-forming area is 10 to 60%.  
     
     
         17 . The process for manufacturing a semiconductor device as claimed in  claim 14  where the interconnect occupancy of the copper interconnects in the device-forming area is 10 to 60%.  
     
     
         18 . The process for manufacturing a semiconductor device as claimed in  claim 13  where the copper interconnects have a thickness of 350 nm or less.  
     
     
         19 . The process for manufacturing a semiconductor device as claimed in  claim 14  where the copper interconnects have a thickness of 350 nm or less.  
     
     
         20 . The process for manufacturing a semiconductor device as claimed in  claim 13  where the interconnect layer is the lowest interconnect layer in the plurality of interconnect layers deposited on the semiconductor substrate.  
     
     
         21 . The process for manufacturing a semiconductor device as claimed in  claim 14  where the interconnect layer is the lowest interconnect layer in the plurality of interconnect layers deposited on the semiconductor substrate.  
     
     
         22 . The process for manufacturing a semiconductor device as claimed in  claim 13  where the interconnect layer further comprises a probe pad area and an interconnect occupancy in the probe pad area is 70 to 90%.  
     
     
         23 . The process for manufacturing a semiconductor device as claimed in  claim 14  where the interconnect layer further comprises a probe pad area and an interconnect, occupancy in the probe pad area is 70 to 90%.