Method of definition of two self-aligned areas at the upper surface of a substrate

Abstract

A method for defining, on the upper surface of a substrate, two self-aligned areas, including the steps of depositing a protective layer; depositing a covering layer; opening the protective and covering layers at a location substantially corresponding to the desired border of the two areas; forming a spacer along the side of the opening, this spacer having a rear portion against said border and an opposite front portion; opening the protective and covering layers behind the rear portion of the spacer; and removing the protection layer to reach the rear portion of the spacer; whereby two self-aligned areas are defined on either side of the spacer length.

What is claimed is:  
     
         1 . A semiconductor device, comprising: 
 a substrate;    a covering layer over the substrate having an edge defining an opening therethrough;    a spacer at the edge defining the opening; and    a contact layer introduced between the substrate and the covering layer and extending to the spacer.    
     
     
         2 . The semiconductor device of  claim 1 , wherein the contact layer is initially undoped.  
     
     
         3 . The semiconductor device of  claim 1 , wherein the spacer has an axis that extends vertically therethrough, and wherein the semiconductor device further comprises an extrinsic base region of a first dopant type in a portion of the substrate on a first side of the axis and an emitter region of a second dopant type in a portion of the substrate on a second side of the axis, opposite to the first side.  
     
     
         4 . The semiconductor device of  claim 1 , wherein the spacer has a length that corresponds to a distance between the extrinsic base region and the emitter region of the transistor.  
     
     
         5 . The semiconductor device of  claim 4 , wherein the dopant source is a P-type dopant, the first dopant type is P-type, and the second dopant type is N-type.  
     
     
         6 . An intermediate product formed during a process of making a semiconductor device, comprising: 
 a substrate;    a covering layer over the substrate having an edge defining an opening therethrough and being doped with a dopant source;    a spacer at the edge defining the opening; and    means for initially separating the dopant source from the substrate.    
     
     
         7 . An intermediate product formed during a process of making an area of a semiconductor device, comprising: 
 a substrate doped with a dopant of a first type;    a protective layer initially undoped and disposed above the substrate;    a covering layer doped with a dopant of a second type that is opposite of the first type and disposed above the protective layer; and    a base region extending through at least a portion of each of the substrate, the protective layer, and the covering layer, and doped with a dopant of the second type.    
     
     
         8 . The An intermediate product formed during a process of making an area of a semiconductor device of  claim 7 , wherein the first type is N-type and the second type is P-type.