Electronic device and a method of manufacturing the same

Abstract

An electronic device comprising: a semiconductor chip having plural electrode pads on one main surface thereof; a wiring board having plural connection parts; and plural salient electrodes disposed respectively between the electrode pads of the semiconductor chip and the connection parts of the wiring board to provide electrical connections between the two, the salient electrodes being arranged in an array not providing balance of the semiconductor chip with respect to one main surface of the wiring board, the plural connection parts of the wiring board being arranged at a deeper position than one main surface of the wiring board in a depth direction from the one main surface.

1 . An electronic device comprising: 
 a semiconductor chip having a plurality of electrode pads on one main surface thereof;    a wiring board having a plurality of connection parts on one main surface thereof; and    a plurality of salient electrodes arranged in a line between the electrode pads of the semiconductor chip and the connection parts of the wiring board,    wherein the plural connection parts of the wiring board are located at a deeper position than said one main surface of the wiring board in a depth direction from said one main surface.    
     
     
         2 . An electronic device according to  claim 1 , wherein the wiring board further includes an insulating film formed on said one main surface thereof and an opening formed in the insulating film, and the plural connection parts are disposed in a bottom of the opening.  
     
     
         3 . An electronic device according to  claim 2 , wherein the insulating film is present straddling a peripheral edge of the semiconductor chip.  
     
     
         4 . An electronic device according to  claim 2 , wherein a plane size of the opening is smaller than that of the semiconductor chip, while a plane size of the insulating film is larger than that of the semiconductor chip.  
     
     
         5 . An electronic device according to  claim 1 , wherein the semiconductor chip is bonded to the wiring board through a bonding resin, and the salient electrodes are compression-bonded to the connection parts of the wiring board.  
     
     
         6 . An electronic device according to  claim 5 , wherein the bonding resin is an anisotropic conductive resin comprising an insulating resin with a large number of conductive particles mixed therein.  
     
     
         7 . An electronic device according to  claim 1 , wherein the plural salient electrodes are stud bumps.  
     
     
         8 . An electronic device according to  claim 1 , wherein the plural salient electrodes are solder bumps.  
     
     
         9 . An electronic device according to  claim 1 , wherein the wiring board has a multi-layer interconnection structure, and the plural connection parts thereof are respectively portions of plural lines formed on a top wiring layer of the wiring board.  
     
     
         10 . An electronic device according to  claim 1 , wherein the semiconductor chip is formed in a square or rectangular shape in plan, and the plural salient electrodes are disposed in any of three areas obtained by dividing said one main surface of the semiconductor chip into three equal areas.  
     
     
         11 . An electronic device according to  claim 10 , wherein a memory array is formed on the other two areas than the area where the salient electrodes are disposed out of the three areas on said one main surface of the semiconductor chip.  
     
     
         12 . An electronic device according to  claim 1 , wherein the plural salient electrodes are not arranged in a direction perpendicular to the direction in which they are arranged.  
     
     
         13 . A method of manufacturing an electronic device, comprising the steps of: 
 providing a semiconductor chip, the semiconductor chip having a plurality of electrode pads arranged in a line in one direction on one main surface of the semiconductor chip and a plurality of salient electrodes disposed respectively on the electrode pads, and a wiring board, the wiring board having a plurality of connection parts arranged correspondingly to the plural salient electrodes at a deeper position than one main surface of the wiring board in a depth direction of said one main surface; and    interposing a bonding resin between said one main surface of the wiring board and said one main surface of the semiconductor chip and compression-bonding the semiconductor chip to said one main surface of the wiring board to electrically connect the salient electrodes of the semiconductor chip respectively to the connection parts of the wiring board.    
     
     
         14 . A method according to  claim 13 , wherein the wiring board further has an insulating film formed on said one main surface thereof and an opening formed in the insulating film, and the plural connection parts are disposed in a bottom of the opening.  
     
     
         15 . A method according to  claim 14 , wherein the insulating film is present straddling a peripheral edge of the semiconductor chip.  
     
     
         16 . A method according to  claim 14 , wherein a plane size of the opening is smaller than that of the semiconductor chip, while a plane size of the insulating film is larger than that of the semiconductor chip.  
     
     
         17 . An electronic device comprising: 
 a first semiconductor chip having a plurality of first electrode pads arranged at a first array pitch on one main surface of the chip;    a second semiconductor chip having a plurality of second electrode pads arranged at a second array pitch smaller than the first array pitch on one main surface of the chip;    a wiring board having in a first area of one main surface thereof a plurality of first connection parts arranged correspondingly to the plural first electrode pads and in a second area of said one main surface different from the first area a plurality of second connection parts arranged correspondingly to the plural second electrode pads;    a plurality of first salient electrodes disposed respectively between the first electrode pads and the first connection parts and providing electric connections between the two; and    a plurality of second salient electrodes disposed respectively between the second electrode pads and the first connection parts and providing electric connections between the two;    the plural first connection parts and the plural second connection parts being disposed at a deeper position than said one main surface of the wiring board in a depth direction from said one main surface, and    the plural second salient electrodes being of a multi-stage bump structure having a larger number of stages than the plural first salient electrodes.    
     
     
         18 . An electronic device according to  claim 17 , wherein the wiring board further has an insulating film formed on said one main surface thereof, a first opening formed in the insulating film in the first area of said one main surface thereof, and a second opening formed in the insulating film in the second area of said one main surface thereof, the plural first connection parts are disposed in a bottom of the first opening, and the plural second connection parts are disposed in a bottom of the second opening.  
     
     
         19 . An electronic device according to  claim 17 , wherein the second salient electrodes are each of a multi-stage bump structure having a base bump connected to each of the second electrode pads of the second semiconductor chip and a stack bump stacked on the base bumps.  
     
     
         20 . An electronic device according to  claim 17 , wherein the second salient electrodes are each of a multi-stage bump structure having a base bump connected to each of the second electrode pads of the second semiconductor chip, a first stack bump stacked on the base bump, and a second stack bump stacked on the first stack bump.  
     
     
         21 . An electronic device according to  claim 17 , wherein the first and second salient electrodes are stud bumps.  
     
     
         22 . An electronic device according to  claim 17 , wherein the wiring board has a multi-layer interconnection structure, and the plural first and second connection parts thereof are respectively portions of plural lines formed on a top wiring layer of the wiring board.  
     
     
         23 . An electronic device according to  claim 17 , wherein the first and second semiconductor chips are bonded to the wiring board through a bonding resin.  
     
     
         24 . An electronic device according to  claim 23 , wherein the bonding resin is an anisotropic conductive resin comprising an insulating resin with a large number of conductive particles mixed therein.  
     
     
         25 . A method of manufacturing an electronic device, comprising the steps of: 
 providing: a first semiconductor chip having a plurality of first electrode pads arranged at a first array pitch on one main surface thereof and a plurality of first salient electrodes connected respectively to the first electrode pads; a second semiconductor chip having a plurality of second electrode pads arranged at a second array pitch smaller than the first array pitch on one main surface thereof and a plurality of second salient electrodes connected respectively to the second electrode pads and having a multi-stage bump structure larger in the number of stages than the first salient electrodes; and a wiring board having an insulating film formed on one main surface thereof, a first opening formed in the insulating film in a first area of said one main surface, a second opening formed in the insulating film in a second area different from the first area of said one main surface, a plurality of first connection parts arranged in a bottom of the first opening correspondingly to the plural first salient electrodes, and a plurality of second connection parts arranged in a bottom of the second opening correspondingly to the plural second salient electrodes;    interposing a first bonding resin between the first area of said one main surface of the wiring board and said one main surface of the first semiconductor chip and compression-bonding the first semiconductor chip to the first area of said one main surface of the wiring board to electrically connect the first salient electrodes respectively to the first connection parts; and    interposing a second bonding resin between the second area of said one main surface of the wiring board and said one main surface of the second semiconductor chip and compression-bonding the second semiconductor chip to the second area of said one main surface of the wiring board to electrically connect the second salient electrodes respectively to the second connection parts.    
     
     
         26 . An electronic device comprising: 
 a first semiconductor chip having a first electrode pad on one main surface thereof;    a second semiconductor chip having a second electrode pad on one main surface thereof, the second electrode pad having a plane area smaller than that of the first electrode pad;    a wiring board having: an insulating film formed on one main surface thereof; a first opening formed in the insulating film in a first area of said one main surface; a second opening formed in the insulating film in a second area different from the first area of said one main surface; a first connection part disposed in a bottom of the first opening; and a second connection part disposed in a bottom of the second opening;    a first salient electrode disposed between the first electrode pad and the first connection part to provide an electrical connection between the two; and    a second salient electrode disposed between the second electrode pad and the second connection part to provide an electrical connection between the two,    wherein the second salient electrode has a multi-stage bump structure larger in the number of stages than the first salient electrode.    
     
     
         27 . An electronic device comprising: 
 a semiconductor chip having an electrode pad on one main surface thereof;    a wiring board having a connection part in a surface layer of one main surface thereof; and    a salient electrode disposed between the electrode pad of the semiconductor chip and the connection part of the wiring board to provide an electrical connection between the two,    the connection part of the wiring board being disposed at a deeper position than said one main surface of the wiring board in a depth direction from said one main surface, and    the salient electrode having a multi-stage bump structure.    
     
     
         28 . An electronic device comprising: 
 a semiconductor chip having an electrode pad on one main surface thereof;    a wiring board having an insulating film formed on one main surface thereof, an opening formed in the insulating film, and a wiring a portion of which is disposed in a bottom of the opening and the remaining portion of which is covered with the insulating film;    a salient electrode disposed between the electrode pad and the wiring portion to provide an electrical connection between the two; and    a bonding resin interposed between the semiconductor chip and the wiring board and charged into the interior of the opening,    wherein the thickness of the insulating film present on the remaining portion of the wiring is not larger than 20 μm.    
     
     
         29 . An electronic device comprising: 
 a semiconductor chip;    a plurality of salient electrodes arranged on one main surface of the semiconductor chip;    a wiring board;    an opening formed in one main surface of the wiring board; and    a plurality of connection parts formed in a bottom of the opening and connected to the plural salient electrodes respectively,    the plural salient electrodes being disposed along a first center line on said one main surface of the semiconductor chip.    
     
     
         30 . An electronic device comprising: 
 a semiconductor chip;    a plurality of salient electrodes arranged on one main surface of the semiconductor chip;    a wiring board;    an opening formed in one main surface of the wiring board; and    a plurality of connection parts formed in a bottom of the opening and connected to the salient electrodes respectively,    the plural salient electrodes being arranged along a first straight line on said one main surface of the semiconductor chip.    
     
     
         31 . An electronic device according to  claim 30 , wherein said one main surface of the semiconductor chip is rectangular, and the first straight line intersects two short sides of said one main surface of the semiconductor chip.  
     
     
         32 . An electronic device comprising: 
 a semiconductor chip;    a plurality of salient electrodes arranged on one main surface of the semiconductor chip;    a wiring board;    an opening formed in one main surface of the wiring board; and    a plurality of connection parts formed in a bottom of the opening and connected to the salient electrodes respectively,    wherein the center of gravity of the semiconductor chip is not included inside a polygon formed by joining the plural salient electrodes on said one main surface of the semiconductor chip.    
     
     
         33 . An electronic device comprising: 
 a semiconductor chip having a plurality of electrode pads on one main surface thereof;    a wiring board having a plurality of connection parts exposed on a surface thereof; and    a plurality of salient electrodes arranged in a line between the electrode pads of the semiconductor chip and the connection parts of the wiring board,    wherein said connection parts of the wiring board are located at a deeper position than one main surface of the wiring board in a depth direction from said one main surface, and    wherein the semiconductor chip is formed in a quadrilateral shape in plan, and said salient electrodes are disposed in any of three areas obtained by dividing said one main surface of the semiconductor chip into three equal areas.    
     
     
         34 . An electronic device according to  claim 33 , wherein a memory array is formed on the other two areas than the area where the salient electrodes are disposed out of the three areas on said one main surface of the semiconductor chip.  
     
     
         35 . An electronic device comprising: 
 a semiconductor chip comprising a main surface, a row of electrode pads and a dynamic random access memory each formed on the main surface, the dynamic random access memory having memory arrays arranged at both sides of the row of electrode pads and input/output circuitry arranged between the row of electrode pads and one of the memory arrays;    a wiring board having a plurality of connection parts exposed on a surface thereof; and    a plurality of salient electrodes formed on the row of electrode pads and electrically connected to the connection parts, respectively;    wherein the connection parts are located at a deeper position than one main surface of the wiring board in a depth direction from said one main surface of the wiring board.    
     
     
         36 . An electronic device according to  claim 35 , wherein the dynamic random access memory is SDRAM.  
     
     
         37 . An electronic device according to  claim 35 , wherein the semiconductor chip is formed in a quadrilateral shape in plan, and the salient electrodes are disposed in a center area of three areas obtained by dividing said one main surface of the semiconductor chip into three equal areas.  
     
     
         38 . An electronic device according to  claim 35 , wherein each said connection part has a recess, and the respective salient electrode connected thereto has a portion received in said recess.  
     
     
         39 . An electronic device according to  claim 38 , wherein the recess of each connection part is formed by an elastic deformation of the connection part and the wiring board.  
     
     
         40 . An electronic device according to  claim 39 , wherein the semiconductor chip is formed in a quadrilateral shape in plan, and the salient electrodes are disposed in a center area of three areas obtained by dividing one main surface of the semiconductor chip into three equal areas.  
     
     
         41 . An electronic device according to  claim 40 , wherein the dynamic random access memory is SDRAM.