Pin-assignment method for integrated circuit packages to increase the electro-static discharge protective capability thereof

Abstract

A pin-assignment method is provided for use on an IC package to arrange pin connections. The pin-assignment method can allow an improvement in the electro-static discharge (ESD) protection capability for the IC chip packed in the IC package. Specifically, the pin-assignment method organizes the no-connect pins of the IC package into groups and then assigns each of the two pins that bound each no-connect pin group to be connected to a power bus of the IC chip. This allows for an increased ESD protective capability for the no-connect pins. Moreover, the pin-assignment method can simplify the wiring complexity of the IC package.

What is claimed is:  
     
         1 . A pin-assignment method for use on an IC package having a plurality of pins including a number of no-connect pins, said IC package encasing an IC chip having a plurality of bonding pads thereon, said pin-assignment method comprising: 
 organizing said no-connect pins into at least one group; and    assigning the two pins that bound both sides of each no-connect pin group to be connected to power pins.    
     
     
         2 . The pin-assignment method of  claim 1 , wherein said no-connect pin group includes one single no-connect pin.  
     
     
         3 . The pin-assignment method of  claim 1 , wherein said no-connect pin group includes a number of consecutive no-connect pins.  
     
     
         4 . The pin-assignment method of  claim 3 , wherein said IC package has four sides and four corners, and said group of consecutive no-connect pins are all arranged on one side of said IC package.  
     
     
         5 . The pin-assignment method of  claim 3 , wherein said IC package has four sides and four corners, and at least two no-connect pins in said group of consecutive no-connect pins are arranged on different sides of said IC package at one corner.  
     
     
         6 . The pin-assignment method of  claim 1 , wherein said IC package includes a plastic compound for encasing the IC chip.  
     
     
         7 . The pin-assignment method of  claim 1 , wherein said IC package includes a resin compound for encasing the IC chip.  
     
     
         8 . The pin-assignment method of  claim 1 , wherein said IC package is a quad flat package.  
     
     
         9 . The pin-assignment method of  claim 1 , wherein said power pin is a V DD  pin.  
     
     
         10 . The pin-assignment method of  claim 1 , wherein said power pin is a ground pin GND.  
     
     
         11 . The pin-assignment method of  claim 1 , wherein the two pins bounding each no-connect pin group are wired respectively to a neighboring pair of the bonding pads on the IC chip.  
     
     
         12 . The pin-assignment method of  claim 1 , wherein the two pins bounding each no-connect pin group are wired to a common bonding pad on the IC chip.  
     
     
         13 . A pin-assignment method for use on an IC package having more than 100 pins including at least five no-connect pins, said IC package encasing an IC chip having a plurality of bonding pads thereon, said pin-assignment method comprising: 
 organizing said no-connect pins into at least one group; and    assigning the two pins that bound each no-connect pin group to be power pins.    
     
     
         14 . The pin-assignment method of  claim 13 , wherein the sum of said no-connect pin groups consists of no-connect pins only and includes at least 5 no-connect pins.  
     
     
         15 . The pin-assignment method of  claim 13 , wherein the sum of said no-connect pin groups consists of all no-connect pins in said IC package.  
     
     
         16 . The pin-assignment method of  claim 13 , wherein said IC package has more than 200 pins including at least 10 no-connect pins.  
     
     
         17 . The pin-assignment method of  claim 16 , wherein the sum of said no-connect pin groups consists of no-connect pins only and includes at least 10 no-connect pins.  
     
     
         18 . The pin-assignment method of  claim 16 , wherein the sum of said no-connect pin groups consists of all no-connect pins in said IC package.  
     
     
         19 . The pin-assignment method of  claim 16 , wherein said IC package has at least 20 no-connect pins; wherein the sum of said no-connect pin groups consists of no-connect pins only and includes at least 20 no-connect pins.  
     
     
         20 . The pin-assignment method of  claim 16 , wherein said IC package has at least 20 no-connect pins; wherein the sum of said no-connect pin groups consists of all no-connect pins in said IC package.  
     
     
         21 . The pin-assignment method of  claim 13 , wherein said no-connect pin group includes one single no-connect pin.  
     
     
         22 . The pin-assignment method of  claim 13 , wherein said no-connect pin group includes a number of consecutive no-connect pins.  
     
     
         23 . The pin-assignment method of  claim 16 , wherein said IC package has four sides and four corners, and said group of consecutive no-connect pins are arranged on one side of said IC package.  
     
     
         24 . The pin-assignment method of  claim 16 , wherein said IC package has four sides and four corners, and at least two no-connect pins in said group of consecutive no-connect pins are arranged on different sides of said IC package at one corner.  
     
     
         25 . The pin-assignment method of  claim 13 , wherein said IC package includes a plastic compound for encasing the IC chip.  
     
     
         26 . The pin-assignment method of  claim 13 , wherein said IC package includes a resin compound for encasing the IC chip.  
     
     
         27 . The pin-assignment method of  claim 13 , wherein said IC package is a quad flat package.  
     
     
         28 . The pin-assignment method of  claim 13 , wherein said power pin is a power V DD  pin.  
     
     
         29 . The pin-assignment method of  claim 13 , wherein said power pin is a ground pin GND.  
     
     
         30 . The pin-assignment method of  claim 13 , wherein the two pins bounding each no-connect pin group are wired to a neighboring pair of the bonding pads on the IC chip.  
     
     
         31 . The pin-assignment method of  claim 13 , wherein the two pins bounding each no-connect pin group are wired to a common bonding pad on the IC chip.  
     
     
         32 . A pin-assignment method for use on an IC package having a plurality of pins which include a number of active pins and no-connect pins, said IC package encasing an IC chip having a plurality of bonding pads thereon, said pin-assignment method comprising: 
 organizing said no-connect pins into at least one group, wherein each group including either one no-connect pin or a number of consecutive no-connect pins; and    assigning each of the two pins that bound each no-connect pin group to be electrically connected to a power bus and internally wired to a bonding pads on said IC chip.    
     
     
         33 . A pin-assignment method for use on an IC package having a plurality of pins which include a number of active pins and no-connect pins, said IC package encasing an IC chip having a plurality of bonding pads thereon, said pin-assignment method comprising: 
 organizing said no-connect pins into at least one group, wherein each group is formed by either one no-connect pin or a number of consecutive no-connect pins; and    assigning at least a pair of pins that bound a no-connect pin group on two-sides to be electrically connected to a power bus of said IC chip and internally wired to a common one of said bonding pads on said IC chip.