IC test cell with memory output connected to input multiplexer

Abstract

A test cell ( 12 ) provides boundary scan testing in an integrated circuit ( 10 ). The test cell ( 12 ) comprises two memories, a flip-flop ( 24 ) and a latch ( 26 ), for storing test data. A first multiplexer ( 22 ) selectively connects one of a plurality of inputs to the flip-flop ( 24 ). The input-of the latch ( 26 ) is connected to output of the-flip-flop ( 24 ). The output of the latch ( 26 ) is connected to one input of a multiplexer ( 28 ), the second input to the multiplexer ( 28 ) being a data input (DIN) signal. A control bus ( 17 ) is provided for controlling the multiplexers ( 22, 28 ), flip-flop ( 24 ) and latch ( 26 ). The test cell allows input data to be observed and output data to be controlled simultaneously.

What is claimed is:  
     
         1 . A boundary scan test cell for use in conjunction with an integrated circuit containing application logic circuitry comprising: 
 a first memory for storing serial data and transmitting said serial data to other test cells; and    a second memory connected to said first memory for storing output data.    
     
     
         2 . The test cell of  claim 1  and further comprising circuitry connecting said second memory to the application logic.  
     
     
         3 . The test cell of  claim 1  and further comprising circuitry to connect the output of said second memory to the input of the first memory.  
     
     
         4 . The test cell of  claim 1  and further comprising hold circuitry to maintain the output of said second memory at a given state.  
     
     
         5 . The test cell of  claim 1  and further comprising toggle circuitry to alternate the output of said second memory between first and second logic levels.  
     
     
         6 . The test cell of  claim 1  wherein the output of said first memory is connected to the input of said second memory such that said second memory can be loaded with a predetermined logic value.  
     
     
         7 . The test cell of  claim 1  and further comprising circuitry to connect said first memory to an input of the integrated circuit.  
     
     
         8 . The test cell of  claim 1  and further comprising circuitry to connect said second memory to an output of the integrated circuit.  
     
     
         9 . A boundary scan test cell comprising: 
 a first memory;    a first multiplexer for connecting one of a plurality of inputs to said first memory responsive to a first control signal;    a second memory connected to the output of said first memory; and    a second multiplexer for selecting an output from one of a set of inputs to the second multiplexer including the output of said second memory responsive to a second control signal.    
     
     
         10 . The test cell of  claim 9  wherein said first memory comprises a D-type flip-flop.  
     
     
         11 . The test cell of  claim 10  and further comprising clock circuitry for producing a clock signal connected to said D-type flip-flop, such that the output of said first multiplexer is stored in said first memory at each clock pulse.  
     
     
         12 . The test cell of  claim 9  wherein said second memory comprises a D-type latch.  
     
     
         13 . The test cell of  claim 12  and further comprising control circuitry connected to said latch for producing a hold signal responsive to which said latch stores data output from said first memory.  
     
     
         14 . The test cell of  claim 9  wherein said second memory includes inverted and non-inverted outputs, said inverted output connected as one of said inputs to said first multiplexer, such that a toggled output may be produced by the test cell.  
     
     
         15 . The test cell of  claim 9  wherein the output of said first memory is connected as one of said inputs to first multiplexer.  
     
     
         16 . An integrated circuit having boundary scan testing, comprising: 
 application logic circuitry having one or more inputs and one or more outputs;    one or more data inputs for receiving data into the integrated circuit;    one or more data outputs for outputing data from the integrated circuit;    a test data input for receiving test data into the integrated circuit;    one or more input test cells connected between respective data inputs and said application logic circuitry, said input test cells comprising: 
 a first memory for storing serial data; and  
 a second memory connected to said first memory for storing output data.  
   
     
     
         17 . The integrated circuit of  claim 16  and further comprising: 
 one or more output test cells connected between said application logic and respective data outputs, said output test cells comprising: 
 a third memory for storing information;  
 a fourth memory for storing information output from said third memory;  
 a third multiplexer selectively connecting one of a plurality of inputs thereto to said third memory, one of said plurality of inputs being connected to said test data input; and  
 a fourth multiplexer for selectively connecting one of a plurality inputs thereto to said respective data output, the respective output from said application logic and the output of said fourth memory being input to said second multiplexer.  
 
 
     
     
         18 . The integrated circuit of  claim 16  and further comprising one or more output test cells connected between respective data outputs and said application logic circuit, said output test cells comprising: 
 a first memory for storing serial data; and  
 a second memory for storing output data.  
 
     
     
         19 . The integrated circuit of  claim 16  wherein said integrated circuit includes a plurality of input test cells and further comprising circuitry for serially connecting ones of said first memories of input cells.  
     
     
         20 . The integrated circuit of  claim 17  wherein said integrated circuit includes a plurality of output test cells and further comprising circuitry for serially connecting ones of said first memories of said output test cells.  
     
     
         21 . The integrated circuit of  claim 17  and further comprising circuitry for connecting the output of said first memory of one of said input test cells to the input of said first memory of one of said output cells.  
     
     
         22 . The integrated circuit of  claim 16  and further comprising circuitry for producing a binary counting function at the output of said second memories of ones of said input test cells.  
     
     
         23 . The integrated circuit of  claim 17  and further comprising circuitry for producing a binary counting function at the output of said second memories of ones of said output test cells.  
     
     
         24 . A bidirectional test cell for use in an integrated circuit having an input/output pin for transferring data to and from application logic circuitry, comprising: 
 a memory for storing data; and    circuitry to selectively connect the input/output pin to the input of output of said memory responsive to a control signal indicating the desired input or output function.    
     
     
         25 . The bidirectional test cell of  claim 24  and further comprising circuitry connecting the output of said memory to the application logic in response to said control signal indicating an input function.  
     
     
         26 . The bidirectional test cell of  claim 24  and further comprising circuitry connecting the input of said memory to the application logic in response to said control signal indicating an output function.  
     
     
         27 . The bidirectional test cell of  claim 24  wherein said memory comprises a first memory, and further comprises a second memory connected to said first memory.  
     
     
         28 . The bidirectional test cell of  claim 24  wherein said circuitry to selectively connect comprises a tristate device connected between the output of said memory and said input/output pin.  
     
     
         29 . The bidirectional test cell of  claim 28  and further comprising a first multiplexer having an output connected to said buffer for selecting between said output of said memory and an input to said test cell.  
     
     
         30 . The bidirectional test cell of  claim 29  and further comprising a second multiplexer having an output connectable to said memory for selecting between said input to said test cell and an input from said input/output pill.  
     
     
         31 . A method of observing and controlling information input to an output from an integrated circuit containing application logic circuitry comprising the steps of: 
 providing a plurality of test cells having first and second memories, one or more of said test cells connected between the input to the integrated circuit and the application logic and one or more of said test cells connected between the output of said integrated circuit and said application logic;    storing serial data in said first memory;    transmitting serial data between the first memories of the test cells; and    storing output data in said second memory.    
     
     
         32 . The method of  claim 31  and further comprising the step of transferring data from said first memories of the respective cells to the second. memories of said respective cells.  
     
     
         33 . The method of  claim 31  and further comprising the step of transferring data stored in said second memories to the respective test cells to the first memories of said respective test cells.  
     
     
         34 . The method of  claim 31  and further comprising the step of maintaining the output of said second memory at a given state responsive to a control signal.  
     
     
         35 . The method of  claim 31  and further comprising the step of toggling the output of said second memory between first and second logic levels.  
     
     
         36 . The method of  claim 31  and further comprising the step of loading said second memories of the test cells with predetermined logic values.  
     
     
         37 . A method of observing data input to a test cell and controlling data output from the test cell comprising the steps of: 
 selectively connecting one of a plurality of inputs to a first memory responsive to a first control signal;    transferring data from said first memory to said second memory; and    selectively outputting the data stored in said second memory.    
     
     
         38 . A method of testing a logic section on an integrated circuit comprising the steps of: 
 observing inputs to the logic section; and    simultaneously controlling the output to the logic section.    
     
     
         39 . The method of  claim 38  wherein said step of observing inputs comprises the step of selectively storing one of a plurality of inputs in a first memory.  
     
     
         40 . The method of  claim 39  wherein said step of simultaneously controlling the output comprises the step of selectively outputting an input to the logic section of the output of a second memory.  
     
     
         41 . The method of  claim 40  and further comprising the step of transferring data from said first memory to said second memory.  
     
     
         42 . The method of  claim 38  wherein said step of simultaneously controlling the output comprises the step of outputting a stream of alternating logic values to the logic section.  
     
     
         43 . The method of  claim 38  wherein said step of simultaneously controlling the output comprises outputting a predetermined value to the logic section.  
     
     
         44 . The method of  claim 38  wherein said step of simultaneously controlling the output comprises the step of outputting a counting sequence to the logic section.