Metal via contact of a semiconductor device and method for fabricating the same

Abstract

A metal via contact of a semiconductor device and a method for fabricating the same, wherein the method includes sequentially forming a first insulating layer, a low dielectric SOG (Spin On Glass) layer, a second insulating layer and a silicon oxynitride (SiON) layer on a semiconductor substrate, forming a photoresist pattern, using the photoresist pattern as an etching mask and wet etching the silicon oxynitride layer and a portion of the second insulating layer, using the same photoresist pattern as an etching mask and anisotropically etching remainder second insulating layer, the low dielectric SOG layer and the first insulating layer to form a via hole exposing a predetermined portion of the semiconductor substrate, removing the photoresist pattern, using radio frequency (RF) etching to remove a reverse slope of the via hole and forming a metal plug in the via hole.

What is claimed is:  
     
         1 . A semiconductor device comprising: an interlayer insulating layer including a first insulating layer, a low dielectric SOG (Spin On Glass) layer, a second insulating layer and a silicon oxynitride layer formed in that order on a semiconductor substrate; and 
 a metal via contact formed in the interlayer insulating layer, the metal via contact being tapered from a top surface of the interlayer insulating layer to a bottom surface of the interlayer insulating layer and being formed by a sputtering.    
     
     
         2 . The semiconductor device according to  claim 1 , wherein the first and second insulating layers are formed of a CVD (Chemical Vapour Deposition) silicon oxide layer.  
     
     
         3 . The semiconductor device according to  claim 1 , wherein the first and second insulating layers are formed of a PE-TEOS oxide layer.  
     
     
         4 . The semiconductor device according to  claim 1 , wherein the low dielectric layer has a dielectric constant of about 3.7 or less.  
     
     
         5 . The semiconductor device according to  claim 1 , wherein the low dielectric SOG layer is formed of an inorganic SOG including HSQ (Hydro SilsesQuioxane).  
     
     
         6 . The semiconductor device according to  claim 3 , wherein the first insulating layer has a thickness between several hundred to several thousand angstrom.  
     
     
         7 . The semiconductor device according to  claim 3 , wherein the second insulating layer has a thickness between about 1000 to 3000 angstrom.  
     
     
         8 . The semiconductor device according to  claim 1 , wherein the silicon oxynitride layer has a thickness of about several hundred angstrom.  
     
     
         9 . The semiconductor device according to  claim 5 , wherein the low dielectric layer has a thickness of about several hundred angstrom.  
     
     
         10 . A method for fabricating a semiconductor device, the method comprising: 
 sequentially forming a first insulating layer, a low dielectric SOG (Spin On Glass) layer, a second insulating layer and a silicon oxynitride (SiON) layer;    forming a photoresist pattern;    using the photoresist pattern as an etching mask and wet etching the silicon oxynitride layer and a portion of the second insulating layer;    using the same photoresist pattern as an etching mask and anisotropically etching a remaining portion of the second insulating layer, the low dielectric SOG layer and the first insulating layer to form a via hole exposing a predetermined portion of the semiconductor substrate;    removing the photoresist pattern;    radio frequency (RF) etching to remove a reverse slope of the via hole; and    forming a metal plug in the via hole.    
     
     
         11 . The method according to  claim 10 , wherein removing the photoresist pattern is carried out by a process selected from the group consisting of ashing and a combination of ashing and stripping.  
     
     
         12 . The method according to  claim 10 , wherein radio frequency (RF) etching continues until the silicon oxynitride layer is completely removed.  
     
     
         13 . The method according to  claim 10 , wherein forming the metal plug comprises sputtering and heat reflow techniques.  
     
     
         14 . The method according to  claim 13 , wherein the sputtering technique uses aluminium as a sputtering source.  
     
     
         15 . The method according to  claim 13 , wherein radio frequency (RF) etching is carried out in a sputtering apparatus for the metal plug, thereby providing an in-situ process for the radio frequency etching and the metal plug.  
     
     
         16 . The method according to  claim 10 , wherein radio frequency (RF) etching is carried out so as not to enlarge a top width of the via hole beyond an undercut portion.