Atomic layer deposition of capacitor dielectric

Abstract

A capacitor structure is formed over a semiconductor substrate by atomic layer deposition to achieve uniform thickness in memory cell dielectric layers, particularly where the dielectric layer is formed in a container-type capacitor structure. In accordance with several embodiments of the present invention, a process for forming a capacitor structure over a semiconductor substrate is provided. Other embodiments of the present invention relate to processes for forming memory cell capacitor structures, memory cells, and memory cell arrays. Capacitor structures, memory cells, and memory cell arrays are also provided.

What is claimed is:  
     
         1 . A capacitor structure comprising: 
 an insulating layer formed over said semiconductor substrate;    a container formed in said insulating layer;    a lower electrode layer formed along an inner surface of said container;    a dielectric layer formed over said lower electrode layer through an atomic layer deposition process where 
 a first precursor is chemisorbed over a surface of said lower electrode layer,  
 a second precursor is reacted with said chemisorbed precursor to form said dielectric layer, and  
 a substantially flat temperature distribution is maintained across said semiconductor substrate as said first precursor is chemisorbed and said second precursor is reacted with said chemisorbed precursor; and  
   an upper electrode layer formed over said dielectric layer.    
     
     
         2 . A capacitor structure as claimed in  claim 1  wherein said dielectric layer is formed on said lower electrode layer.  
     
     
         3 . A capacitor structure as claimed in  claim 1  wherein said lower electrode layer covers the entire inner surface of said container.  
     
     
         4 . A capacitor structure as claimed in  claim 1  wherein said dielectric layer covers the entire lower electrode layer.  
     
     
         5 . A capacitor structure as claimed in  claim 1  wherein said upper electrode layer covers the entire dielectric layer.  
     
     
         6 . A capacitor structure as claimed in  claim 1  wherein said atomic layer deposition process is characterized by a semiconductor substrate temperature of between about 350° C. to about 700° C. and a pressure of about 1 Torr to about 120 Torr.  
     
     
         7 . A capacitor structure comprising: 
 an insulating layer formed over said semiconductor substrate;    a container formed in said insulating layer;    a lower electrode layer formed along an inner surface of said container;    a dielectric layer formed over said lower electrode layer and an upper surface of said insulating layer through an atomic layer deposition process where 
 a first precursor is chemisorbed over a surface of said lower electrode layer,  
 a second precursor is reacted with said chemisorbed precursor to form said dielectric layer, and  
 a substantially flat temperature distribution is maintained across said semiconductor substrate as said dielectric layer is formed, and said dielectric layer exhibits uniform thickness across said lower electrode layer and said upper surface of said insulating layer;  
   a reoxidized layer formed over said dielectric layer by subjecting said dielectric layer to a reoxidation process, wherein said dielectric layer is formed such that said uniform thickness is sufficient to prevent oxidation of said lower electrode layer as a result of said reoxidation process; and    an upper electrode layer formed over said reoxidized layer.    
     
     
         8 . A capacitor structure as claimed in  claim 7  wherein said dielectric layer is formed in an atomic layer deposition chamber and said reoxidized layer is formed in said chamber or external to said chamber.  
     
     
         9 . A capacitor structure comprising: 
 an insulating layer formed over said semiconductor substrate;    a container formed in said insulating layer;    a lower electrode layer formed along an inner surface of said container;    a silicon nitride dielectric layer formed over said lower electrode layer through an atomic layer deposition process where a silicon-containing precursor is chemisorbed over a surface of said lower electrode layer and a nitrogen-containing precursor is reacted with said chemisorbed silicon-containing precursor to form said silicon nitride dielectric layer; and    an upper electrode layer formed over said dielectric layer.    
     
     
         10 . A capacitor structure as claimed in  claim 9  wherein said silicon-containing precursor is selected from SiCl 4 , SiHCl 3 , SiH 2 Cl 2 , Si 2 H 6 , SiCl 6 , and SiH 4 , and combinations thereof and said nitrogen-containing precursor is selected from NH 3 , N 2 H 2  and combinations thereof.  
     
     
         11 . A capacitor structure comprising: 
 a BPSG insulating layer formed over said semiconductor substrate;    a container formed in said BPSG insulating layer;    an HSG polysilicon lower electrode layer formed along an inner surface of said container;    a silicon nitride dielectric layer formed on said HSG lower electrode layer through an atomic layer deposition process where a silicon-containing precursor is chemisorbed over a surface of said HSG lower electrode layer and a nitrogen-containing precursor is reacted with said chemisorbed silicon-containing precursor to form said silicon nitride dielectric layer;    a reoxidized layer formed over said silicon nitride dielectric layer by subjecting said silicon nitride dielectric layer to a reoxidation process; and    a polysilicon upper electrode layer formed over said reoxidized layer.    
     
     
         12 . A capacitor structure of a memory cell comprising: 
 a semiconductor substrate including a semiconductor structure defining a transistor and a pair of transistor node locations;    a BPSG insulating layer formed over said semiconductor substrate;    a container in said BPSG insulating layer formed over one of said transistor node locations;    an HSG polysilicon lower electrode layer formed along an inner surface of said container;    a silicon nitride dielectric layer formed on said HSG lower electrode layer and over a portion of an upper surface of said BPSG insulating layer through an atomic layer deposition process where 
 said silicon nitride dielectric layer has a thickness of 50 Å or less;  
 a silicon-containing precursor is chemisorbed over a surface of said HSG lower electrode layer and said portion of said upper surface of said BPSG insulating layer,  
 a nitrogen-containing precursor is reacted with said chemisorbed silicon-containing precursor to form said silicon nitride dielectric layer, and  
 said silicon nitride dielectric layer exhibits uniform thickness across said HSG lower electrode layer and said portion of said upper surface of said BPSG insulating layer;  
   a reoxidized layer formed over said silicon nitride dielectric layer by subjecting said silicon nitride dielectric layer to a reoxidation process, wherein said silicon nitride dielectric layer is formed such that said uniform thickness is sufficient to prevent oxidation of said HSG lower electrode layer as a result of said reoxidation process; and    a polysilicon upper electrode layer formed over said reoxidized layer.    
     
     
         13 . A memory cell comprising: 
 a semiconductor substrate including a semiconductor structure defining a transistor and a pairs of transistor node locations;    an insulating layer formed over said semiconductor substrate;    a container in said insulating layer formed over one of said transistor node locations;    a lower electrode layer formed along an inner surface of said container;    a silicon nitride dielectric layer formed over said lower electrode layer and a portion of an upper surface of said insulating layer through an atomic layer deposition process where 
 a silicon-containing precursor is chemisorbed over a surface of said lower electrode layer and said portion of said upper surface of said insulating layer,  
 a nitrogen-containing precursor is reacted with said chemisorbed silicon-containing precursor to form said silicon nitride dielectric layer, and  
 said silicon nitride dielectric layer exhibits uniform thickness across said lower electrode layer and said portion of said upper surface of said insulating layer;  
   a reoxidized layer formed over said dielectric layer by subjecting said dielectric layer to a reoxidation process, wherein said dielectric layer is formed such that said uniform thickness is sufficient to prevent oxidation of said lower electrode layer as a result of said reoxidation process; and    an upper electrode layer formed over said reoxidized layer.    
     
     
         14 . An array of memory cells comprising: 
 a semiconductor substrate including a semiconductor structure defining a plurality of transistors and respective pairs of transistor node locations;    an insulating layer formed over said semiconductor substrate;    respective containers formed in said insulating layer over selected ones of said transistor node locations;    respective lower electrode layers formed along inner surfaces of selected ones of said containers;    respective silicon nitride dielectric layers formed over said lower electrode layer and a portion of an upper surface of said insulating layer through an atomic layer deposition process where 
 a silicon-containing precursor is chemisorbed over a surface of said lower electrode layer and said portion of said upper surface of said insulating layer,  
 a nitrogen-containing precursor is reacted with said chemisorbed silicon-containing precursor to form said silicon nitride dielectric layer, and  
 said silicon nitride dielectric layer exhibits uniform thickness across said lower electrode layer and said portion of said upper surface of said insulating layer;  
   a reoxidized layer formed over said dielectric layer by subjecting said dielectric layer to a reoxidation process, wherein said dielectric layer is formed such that said uniform thickness is sufficient to prevent oxidation of said lower electrode layer as a result of said reoxidation process; and    an upper electrode layer formed over said reoxidized layer.    
     
     
         15 . A capacitor structure as  claim 1  wherein said dielectric layer has a uniform thickness of 50 Å or less.  
     
     
         16 . A capacitor structure as claimed in  claim 7  wherein said dielectric layer has a uniform thickness of 50 Å or less.  
     
     
         17 . A capacitor structure as claimed in  claim 9  wherein said dielectric layer has a uniform thickness of 50 Å or less.  
     
     
         18 . A capacitor structure as claimed in  claim 11  wherein said dielectric layer has a uniform thickness of 50 Å or less.  
     
     
         19 . A capacitor structure as claimed in  claim 12  wherein said dielectric layer has a uniform thickness of 50 Å or less.  
     
     
         20 . A memory cells as claimed in  claim 13  wherein said dielectric layer has a uniform thickness of 50 Å or less.  
     
     
         21 . An array of memory cells as claimed in  claim 14  wherein said dielectric layer has a uniform thickness of 50 Å or less.  
     
     
         22 . A capacitor structure formed over a semiconductor substrate, said capacitor structure comprising: 
 an insulating layer formed over said semiconductor substrate;    a container formed in said insulating layer;    a lower electrode layer formed along an inner surface of said container;    a silicon nitride dielectric layer formed over said lower electrode layer wherein said silicon nitride dielectric layer has a uniform thickness less than 50 Å; and    an upper electrode layer formed over said dielectric layer.    
     
     
         23 . A memory cell comprising: 
 a semiconductor substrate including a semiconductor structure defining a transistor and a pairs of transistor node locations;    an insulating layer formed over said semiconductor substrate;    a container formed in said insulating layer over one of said transistor node locations;    a lower electrode layer formed along an inner surface of said container;    a silicon nitride dielectric layer formed over said lower electrode layer and a portion of an upper surface of said insulating layer through an atomic layer deposition process wherein said silicon nitride dielectric layer has a uniform thickness of 50 Å or less;    a reoxidized layer formed over said dielectric layer; and    an upper electrode layer formed over said reoxidized layer.    
     
     
         24 . A memory cell array comprising: 
 a semiconductor substrate including a semiconductor structure defining a plurality of transistors and respective pairs of transistor node locations;    an insulating layer formed over said semiconductor substrate;    respective containers formed in said insulating layer over selected ones of said transistor node locations;    respective lower electrode layers formed along inner surfaces of selected ones of said containers;    respective silicon nitride dielectric layers formed over said lower electrode layer and a portion of an upper surface of said insulating layer, wherein said dielectric layer has a uniform thickness of 50 Å or less;    a reoxidized layer formed over said dielectric layer; and    an upper electrode layer formed over said reoxidized layer.