High speed memory system

Abstract

A method and structure for implementing a DRAM memory array as a second level cache memory in a computer system. The computer system includes a central processing unit (CPU), a first level SRAM cache memory, a CPU bus coupled to the CPU, and a second level cache memory which includes a DRAM array coupled to the CPU bus. When accessing the DRAM array, row access and column decoding operations are performed in a self-timed asynchronous manner. Predetermined sequences of column select operations are then performed in a synchronous manner with respect to a clock signal. A widened data path is provided to the DRAM array, effectively increasing the data rate of the DRAM array. By operating the DRAM array at a higher data rate than the CPU bus, additional time is provided for precharging the DRAM array. As a result, the precharging of the DRAM array is transparent to the CPU bus. A structure and method control the refresh and internal operations of the DRAM array.

What is claimed is:  
     
         1 . A next level cache memory which is coupled to a central processing unit (CPU) by a bus, the CPU including a first level cache memory, the next level cache memory comprising: 
 a data buffer memory having an input port and an output port, the output port having a first width which enables the output port to simultaneously transfer a first number of data values, the input port having a second width which enables the input port to simultaneously transfer a second number of data values, the first number being greater than the second number, wherein the input port is coupled to the bus; and    a dynamic random access memory (DRAM) array coupled to the output port of the data buffer memory.    
     
     
         2 . The next level cache memory of  claim 1 , wherein the data buffer memory is a multi-depth data buffer, thereby being capable of storing at least one set of write burst data.  
     
     
         3 . The next level cache memory of  claim 1 , wherein the input port and the output port are driven by clock signals of the same frequency.  
     
     
         4 . The next level cache memory of  claim 1 , wherein the DRAM array comprises: 
 an array of DRAM memory cells;    a sense amplifier circuit coupled to the array of DRAM memory cells;    a column selector circuit coupled to the sense amplifier circuit; and    a data amplifier circuit coupled to the column selector circuit, wherein the column selector circuit can selectably isolate and connect the data amplifier circuit to the sense amplifier circuit.    
     
     
         5 . A next level cache memory which is coupled to a central processing unit (CPU) by a bus, the CPU including a first level cache memory, the next level cache memory comprising: 
 a data buffer memory having an input port and an output port, the input port having a first width which enables the input port to simultaneously transfer a first number of data values, the output port having a second width which enables the output port to simultaneously transfer a second number of data values, the first number being greater than the second number, wherein the output port is coupled to the bus; and    a dynamic random access memory (DRAM) array coupled to the input port of the data buffer memory.    
     
     
         6 . The next level cache memory of  claim 5 , wherein the data buffer memory is a multi-depth data buffer, thereby being capable of storing at least one set of read burst data.  
     
     
         7 . The next level cache memory of  claim 5 , wherein the input port and the output port are driven by clock signals of the same frequency.  
     
     
         8 . The next level cache memory of  claim 5 , wherein the DRAM array comprises: 
 an array of DRAM memory cells;    a sense amplifier circuit coupled to the array of DRAM memory cells;    a column selector circuit coupled to the sense amplifier circuit; and    a data amplifier circuit coupled to the column selector circuit, wherein the column selector circuit can selectably isolate or connect the data amplifier circuit to the sense amplifier circuit.    
     
     
         9 . A next level cache memory which is coupled to a central processing unit (CPU) by a bus, the CPU including a first level cache memory, the next level cache memory comprising:. 
 a dynamic random access memory (DRAM) array having a plurality of terminals coupled to the bus, wherein a first terminal is connected to receive a first signal from the CPU indicating the start of a new transaction and a second terminal is connected to receive a second signal from the CPU which identifies the new transaction as a read transaction or a write transaction.    
     
     
         10 . The next level cache memory of  claim 9 , wherein the first signal is an address strobe input signal initiated by the CPU.  
     
     
         11 . The next level cache memory of  claim 10 , wherein the first signal is generated by the CPU is compatible with a pipelined burst static random access memory (PBSRAM) protocol.  
     
     
         12 . A next level cache memory which is coupled to a central processing unit (CPU) and a system controller, the CPU including a first level cache memory, the next level cache memory comprising: 
 a dynamic random access memory (DRAM) array having a plurality of terminals coupled to the system controller, wherein a first terminal is connected to receive a first signal from the system controller indicating the start of a new transaction and second and third terminals are connected to receive second and third signals, respectively, from the system controller, wherein the second and third signals identify the new transaction as a read transaction or a write transaction.    
     
     
         13 . The next level cache memory of  claim 12 , wherein the first signal is an address strobe input signal initiated by the system controller.  
     
     
         14 . The next level cache memory of  claim 13 , wherein the first signal is generated by the system controller is compatible with a pipelined burst static random access memory (PBSRAM) protocol.  
     
     
         15 . The next level cache memory of  claim 12 , wherein the second and third signals are compatible with a pipelined burst static random access memory (PBSRAM) protocol.  
     
     
         16 . The next level cache memory of  claim 15 , wherein the second signal is a byte write enable (BWE#) input signal and the third signal is a global write (GW#) input signal.  
     
     
         17 . A next level cache memory which is coupled to a central processing unit (CPU) and a system controller, the CPU including a first level cache memory, the next level cache memory comprising: 
 a dynamic random access memory (DRAM) array having a terminal coupled to the system controller, wherein at least one signal is provided to the terminal to implement a protocol to manage refresh operations within the DRAM array.    
     
     
         18 . The next level cache memory of  claim 17 , wherein an edge transition of the signal in a first direction indicates a pending refresh operation and an edge transition of the signal in a second direction indicates completion of a refresh operation.  
     
     
         19 . The next level cache memory of  claim 17 , further comprising means in the system controller for sampling the signal at the beginning of read and write transactions of the DRAM array.  
     
     
         20 . The next level cache memory of  claim 17 , wherein the DRAM array further comprises: 
 a master DRAM which has the terminal; and    at least one slave DRAM, each having a terminal coupled to the terminal of the master DRAM chip.    
     
     
         21 . The next level cache memory of  claim 20 , wherein the terminal of the DRAM array is an input/output pin.  
     
     
         22 . The next level cache memory of  claim 21 , wherein the master DRAM and the system controller perform a handshake operation using the signal.  
     
     
         23 . The next level cache memory of  claim 22 , wherein each slave DRAM further comprises an input circuit which monitors the state of the signal to control the refresh and internal operations of the corresponding slave DRAM.  
     
     
         24 . The next level cache memory of  claim 17 , wherein the system controller includes circuitry for providing the signal to the DRAM array.  
     
     
         25 . The next level cache memory of  claim 17 , wherein the signal has at least one edge or state driven by the DRAM array which indicates a pending refresh or internal operation.  
     
     
         26 . The next level cache memory of  claim 25 , wherein the signal further has at least one edge or state driven by the system controller which indicates allowance of the pending refresh or internal operation.  
     
     
         27 . The next level cache memory of  claim 25 , further comprising a second signal which has at least one edge or state driven by the system controller which indicates allowance of said refresh or internal operation.  
     
     
         28 . A method of using a dynamic random access memory (DRAM) array as a next level cache memory in a computer system having a central processing unit (CPU) and a first level cache memory coupled to a bus, the method comprising the steps of: 
 connecting an input port of a data buffer memory to the DRAM array;    connecting an output port of the data buffer memory to the bus;    operating the output port of the data buffer memory in response to a first clock signal;    operating the input port of the data buffer memory in response to a second clock signal;    transmitting a plurality of data values from the DRAM array to the input port of the data buffer memory during each cycle of the second clock signal; and    transmitting a single data value from the output port of the data buffer memory to the bus during each cycle of the first clock signal.    
     
     
         29 . The method of  claim 28 , wherein the first and second clock signals each have the same frequency.  
     
     
         30 . The method of  claim 28 , further comprising the step of precharging the DRAM array during the step of transmitting a single data value.  
     
     
         31 . The method of  claim 30 , wherein the DRAM array comprises an array of DRAM memory cells, a sense amplifier circuit coupled to the array of DRAM memory cells, column selector circuit coupled to the sense amplifier circuit, and a data amplifier circuit coupled to the column selector circuit, the method further comprising the steps of: 
 reading the plurality of data values from the array of DRAM memory cells to the data amplifier circuit through the sense amplifier circuit and the column selector circuit;    disconnecting the data amplifier circuit from the sense amplifier circuit using the column selector circuit; and then    precharging the DRAM array at the same time that the plurality of data values are transmitted to the input port of the data buffer memory.    
     
     
         32 . A method of using a dynamic random access memory (DRAM) array as a next level cache memory in a computer system having a central processing unit (CPU) and a first level cache memory coupled to a bus, the method comprising the steps of: 
 connecting an input port of a data buffer memory to the bus;    connecting an output port of the data buffer memory to the DRAM array;    operating the input port of the data buffer memory in response to a first clock signal.;    operating the output port of the data buffer memory in response to a second clock signal;    transmitting a single data value from the bus to the input port of the data buffer memory during each cycle of the first clock signal; and    transmitting a plurality of data values from the output port of the data buffer memory to the DRAM array during each cycle of the second clock signal.    
     
     
         33 . The method of  claim 32 , wherein the first and second clock signals each have the same frequency.  
     
     
         34 . The method of  claim 32 , further comprising the step of precharging the DRAM array during the step of transmitting a single data value.  
     
     
         35 . A method of controlling refresh and internal operations of a dynamic random access memory (DRAM) array used as a next level cache memory in a computer system which includes a central processing unit (CPU) having a first level cache memory and a system controller, the method comprising the steps of: 
 transmitting a first signal from the CPU to the DRAM array to initiate a transaction requested by the CPU;    transmitting a second signal from the system controller to the DRAM array to initiate a transaction requested by the controller;    coupling a terminal of the DRAM array to the system controller; and    providing a third signal to the terminal to implement a protocol to manage refresh and internal operations within the DRAM array.    
     
     
         36 . The method of  claim 35 , wherein the third signal has a first state and a second state, wherein a transition from the first state to the second state indicates a pending refresh or internal operation, and a transition from the second state to the first state indicates a completed refresh or internal operation, the method further comprising the steps of: 
 monitoring the first and second signals to determine when the first signal or the second signal is asserted; and determining    determining the state of the third signal when either the first signal or the second signal is asserted.    
     
     
         37 . The method of  claim 36 , further comprising the steps of: 
 performing and transactions requested by the CPU and by the controller to completion if the third signal is in the first state when either the first signal or the second signal is asserted.    
     
     
         38 . The method of  claim 37 , further comprising the steps of: 
 performing a transaction requested by the controller to completion and then performing a refresh or internal operation if the third signal is in the second state and has been in the second state for less than a first predetermined time period when the first signal is asserted; and    performing a refresh or internal operation and delaying the CPU-requested transaction if the third signal has been in the second state for at least the first predetermined time period when the first signal is asserted.    
     
     
         39 . The method of  claim 38 , further comprising the step of performing a refresh or internal operation and delaying a transaction requested by the controller if the third signal is in the second state when the second signal is asserted.  
     
     
         40 . The method of  claim 38 , further comprising the steps of: 
 performing a transaction requested by the controller to completion and then performing a refresh or internal operation if the third signal is in the second state and has been in the second state for less than a first predetermined time period when the second signal is asserted; and    performing a refresh or internal operation and delaying the controller-requested transaction if the third signal has been in the second state for at least the first predetermined time period when the second signal is asserted.    
     
     
         41 . The method of  claim 37 , further comprising the steps of: 
 performing a refresh or internal operation and delaying a transaction requested by the CPU if the third signal is in the second state when the first signal is asserted.    
     
     
         42 . The method of  claim 35 , wherein the DRAM array comprises a master DRAM device and one or more slave DRAM devices, the method further comprising the steps of: 
 providing the first, second and third signals to the master DRAM device and the slave DRAM devices;    transmitting the third signal between the master DRAM device and the system controller;    sampling the third signal with the slave DRAM devices; and    controlling the refresh and internal operations of the slave DRAM devices in response to the third signal.    
     
     
         43 . The method of  claim 35 , further comprising the step of driving the third signal with the system controller.  
     
     
         44 . The method of  claim 35 , further comprising the step of driving the third signal with the DRAM array to indicate pending refresh or internal operations.  
     
     
         45 . The method of  claim 44 , further comprising the step of driving the third signal with the system controller to indicate allowance of refresh or internal operations.  
     
     
         46 . The method of  claim 44 , further comprising the step of driving a fourth signal with the system controller to indicate allowance of refresh or internal operations.