Method for fabricating semiconductor memory device

Abstract

A semiconductor memory device is provided which prevents a lifting phenomenon by improving an adhesive strength between an upper electrode and an interlayer insulating layer. The semiconductor memory device includes a capacitor formed on a semiconductor substrate, wherein the capacitor includes a lower electrode, a dielectric layer and an upper electrode; an adhesion layer formed on the upper -electrode; an interlayer insulating layer covering the capacitor, wherein a portion of the interlayer insulating layer is in contact with the adhesion layer; and a contact hole, formed within the interlayer insulating layer, whose bottom exposes the upper electrode and whose sidewalls expose the interlayer insulating layer and the adhesion layer.

What is claimed is:  
     
         1 . A semiconductor memory device, comprising: 
 a capacitor formed on a semiconductor substrate, wherein the capacitor includes a lower electrode, a dielectric layer and an upper electrode;    an adhesion layer formed on the upper electrode;    an interlayer insulating layer covering the capacitor, wherein a portion of the interlayer insulating layer is in contact with the adhesion layer; and    a contact hole, formed within the interlayer insulating layer, whose bottom exposes the upper electrode and whose sidewalls expose the interlayer insulating layer and the adhesion layer.    
     
     
         2 . The semiconductor memory device as recited in  claim 1 , wherein the adhesion layer is formed with a material selected from the group consisting of Ti, Ta, Zr, Hf, TiO 2 , Ta 2 O 5 , ZrO 2  and HfO 2 .  
     
     
         3 . The semiconductor memory device as recited in  claim 2 , wherein the dielectric layer is a ferroelectric layer.  
     
     
         4 . A method for fabricating a semiconductor memory device, comprising steps of: 
 a) forming a capacitor by stacking a lower electrode, a dielectric layer and an upper electrode on a semiconductor substrate;    b) forming an adhesion layer and a hard mask layer on the upper electrode;    c) etching the adhesion layer and the upper electrode by using the hard mask layer as an etching mask;    d) removing the hard mask layer to expose the adhesion layer;    e) patterning the dielectric layer and the lower electrode;    f) forming an interlayer insulating layer on an entire structure to bring a portion of the interlayer insulating layer into contact with the adhesion layer; and    g) selectively etching the interlayer insulating layer and the adhesion layer to form a contact hole, a bottom of said contact hole exposing the upper electrode and sidewalls of said contact hole exposing the interlayer insulating layer and the adhesion layer.    
     
     
         5 . The method as recited in  claim 4 , wherein the dielectric layer is a ferroelectric layer.  
     
     
         6 . The method as recited in  claim 5 , further comprising, after the step e), a step of carrying out a thermal treatment at an oxygen atmosphere.  
     
     
         7 . The method as recited in  claim 4 , wherein the adhesion layer is formed with a material selected from the group consisting of TiO 2 , Ta 2 ,O 5 , ZrO 2  and HfO 2 .  
     
     
         8 . The method as recited in  claim 7 , further comprising, after the step e), a step of carrying out one of a rapid thermal process, a plasma process and an ozone process.