Non volatile memory and data processor

Abstract

The present invention aims to shorten the time required to charge and discharge a bit line connected with each of non-volatile memory cells and speed up the reading of memory information from the non-volatile memory cell. With a main/sub bit line structure as a premise, a clamp voltage is supplied from each of voltage supply elements (QPC 0 through QPCm) to each of main bit lines (MB 0 through MBm) during a period prior to and subsequent to a read operation for a non-volatile memory cell (MC). In parallel with it, sub bit lines (LB 00 through LBkm) are respectively discharged by discharge elements (QD 00 through QDkm). There is no need to precharge the main bit line from a ground level upon the operation of reading memory information and a read operation time can hence be shortened. Thus, a non-volatile memory becomes fast in operating speed. Since the drain (sub bit line) of the memory cell is maintained at a ground potential, no memory disturb problem arises.

What is claimed is:  
     
         1 . A semiconductor device, comprising: 
 an electrically programmable non-volatile memory including: 
 a plurality of non-volatile memory cells;  
 word lines respectively connected to select terminals of the non-volatile memory cells;  
 sub bit lines respectively connected to data terminals of the non-volatile memory cells;  
 main bit lines;  
 sub bit line selection switch elements which selectively connect the sub bit lines to the main bit lines;  
 a sense amplifier connected to the main bit lines via column switch elements; and  
 voltage supply elements each of which supplies a predetermined clamp voltage to each of the main bit lines,  
   wherein the clamp voltage is a predetermined level between a high-level side attainment level outputted from the sense amplifier and a low-level side attainment level outputted therefrom, and each of the voltage supply elements supplies the clamp voltage to the corresponding main bit line during at least a period prior to and subsequent to a read operation for each of the non-volatile memory cells.    
     
     
         2 . The semiconductor device according to  claim 1 , wherein the clamp voltage is a voltage approximately equal to a criterion level of the sense amplifier.  
     
     
         3 . The semiconductor device according to  claim 1 , wherein the clamp voltage is a voltage higher than the criterion level of the sense amplifier.  
     
     
         4 . The semiconductor device according to  claim 3 , wherein the voltage supply element stops the operation of supplying the clamp voltage during a period of a read operation for the non-volatile memory cell.  
     
     
         5 . The semiconductor device according to  claim 4 , wherein the clamp voltage is supplied to the main bit line during the period prior to and subsequent to the read operation when each of the sub bit line selection switch elements is brought to an off state.  
     
     
         6 . The semiconductor device according to  claim 5 , further including discharge elements each of which discharges the sub bit line when the sub bit line selection switch element is brought to the off state.  
     
     
         7 . The semiconductor device according to  claim 6 , wherein the discharge elements are provided every sub bit lines.  
     
     
         8 . The semiconductor device according to  claim 3 , wherein the voltage supply elements are provided every main bit lines selected by the column switch elements.  
     
     
         9 . The semiconductor device according to  claim 3 , wherein the voltage supply elements are provided for a common data line commonly connected to the column switch elements.  
     
     
         10 . The semiconductor device according to  claim 3 , wherein the sub bit line selection switches are capable of being switch-controlled separately every main bit lines sharing the common data line commonly connected to the column switch elements, and the sub bit line selection switch connected to the main bit line selected by the corresponding column switch element is brought to an on state upon a read operation.  
     
     
         11 . The semiconductor device according to  claim 3 , further including source line connection selection switch elements which selectively connect source lines of a plurality of the non-volatile memory cells to a common source line every main bit lines sharing the common data line commonly connected to the column switch elements, wherein the source line connection selection switch element connected to the non-volatile memory cell for each main bit line selected by the corresponding column switch element is brought to an on state upon the read operation.  
     
     
         12 . The semiconductor device according to  claim 1 , wherein the sense amplifier is configured as a current sense type circuit which supplies a current smaller than a current flowing in the corresponding non-volatile memory cell held on when selected by each of the word lines, to each bit line and detects a change in bit line level with respect to the criterion level.  
     
     
         13 . A data processor, comprising: 
 an electrically programmable non-volatile memory; and    a CPU accessible to the non-volatile memory,    wherein the non-volatile memory includes a plurality of non-volatile memory cells, word lines respectively connected to select terminals of the non-volatile memory cells, sub bit lines respectively connected to data terminals of the non-volatile memory cells, main bit lines, sub bit line selection switch elements which selectively connect the sub bit lines to the main bit lines, a sense amplifier connected to the main bit lines via column switch elements, voltage supply elements each of which supplies a predetermined clamp voltage to each main bit line, and discharge elements which discharge the sub bit lines,    wherein each of the voltage supply elements supplies the clamp voltage to the corresponding main bit line before the start and end of a read operation effected on each non-volatile memory cell, and    wherein the discharge elements discharge the sub bit lines after the completion of the read operation.    
     
     
         14 . The data processor according to  claim 13 , wherein a timing provided to supply the clamp voltage to each of the main bit lines after the completion of the read operation is set after the sub bit line selection switch element has been brought to an off state.  
     
     
         15 . The data processor according to  claim 14 , wherein a timing provided to discharge each of the sub bit lines after the completion of the read operation is set after the sub bit line selection switch element has been brought to an off state.  
     
     
         16 . The semiconductor device according to  claim 2 , wherein each of the voltage supply elements stops the operation of supplying the clamp voltage during a period of a read operation for the non-volatile memory cell.  
     
     
         17 . The semiconductor device according to  claim 16 , wherein the clamp voltage is supplied to the main bit line during the period prior to and subsequent to the read operation when each of the sub bit line selection switch elements is brought to an off state.  
     
     
         18 . The semiconductor device according to  claim 17 , further including discharge elements each of which discharges the sub bit line when the sub bit line selection switch element is brought to the off state.  
     
     
         19 . The semiconductor device according to  claim 18 , wherein the discharge elements are provided every sub bit lines.  
     
     
         20 . The semiconductor device according to  claim 2 , wherein the voltage supply elements are provided every main bit lines selected by the column switch elements.  
     
     
         21 . The semiconductor device according to  claim 2 , wherein the voltage supply elements are provided for a common data line commonly connected to the column switch elements.  
     
     
         22 . The semiconductor device according to  claim 2 , wherein the sub bit line selection switches are capable of being switch-controlled separately every main bit lines sharing the common data line commonly connected to the column switch elements, and the sub bit line selection switch connected to the main bit line selected by the corresponding column switch element is brought to an on state upon a read operation.  
     
     
         23 . The semiconductor device according to  claim 2 , further including source line connection selection switch elements which selectively connect source lines of a plurality of the non-volatile memory cells to a common source line every main bit lines sharing the common data line commonly connected to the column switch elements, wherein the source line connection selection switch element connected to the non-volatile memory cell for each main bit line selected by the corresponding column switch element is brought to an on state upon the read operation.