Semiconductor device and method for driving the same

Abstract

A nonvolatile semiconductor storage element, which is provided with a floating gate electrode, and a dielectric capacitor and a ferroelectric capacitor both connected to the floating gate electrode. By applying voltage between a first polarization voltage supplying terminal and a second polarization voltage supplying terminal, polarization serving as information is generated in the ferroelectric film of the ferroelectric capacitor. Additionally, when a read-out voltage is applied between the ground terminal and the power source voltage terminal that are in connection with the source and drain regions, the MISFET is turned either on or off in correspondence to the state of the charge held in the floating gate electrode, and thus information within the floating gate electrode is read out.

What is claimed is:  
     
         1 . A nonvolatile memory, comprising: 
 a transistor having a source region, a drain region and a floating gate electrode;    a dielectric capacitor, which is connected to the floating gate electrode and has a dielectric layer;    a ferroelectric capacitor, which is connected to the floating gate electrode and has a ferroelectric layer; and    first and second polarization voltage application terminals, which are connected to the dielectric capacitor and the ferroelectric capacitor, respectively, and which apply voltage for generating polarization to the ferroelectric capacitor,    wherein the dielectric capacitor is composed of a polarization gate electrode connected by the floating gate electrode, the dielectric layer and the first polarization voltage application terminals.    
     
     
         2 . The nonvolatile memory according to  claim 1 , wherein the dielectric layer of the dielectric capacitor is provided on the floating gate electrode; 
 wherein a polarization gate electrode is further provided on the dielectric layer;    wherein the first polarization voltage application terminal is connected to the polarization gate electrode; and    wherein the dielectric capacitor is configured having the floating gate electrode as a lower electrode, and the polarization gate electrode as an upper electrode.    
     
     
         3 . The nonvolatile memory according to  claim 1 , wherein the ferroelectric capacitor has a lower electrode that is provided above the floating gate electrode, and an upper electrode that is in opposition to said lower electrode, the ferroelectric layer being sandwiched between the lower electrode and the upper electrode; and 
 wherein the second polarization voltage application terminal is connected to the upper electrode of the ferroelectric capacitor.    
     
     
         4 . The nonvolatile according to  claim 1 , further comprising a pass transistor that is connected to either the source region or the drain region and carries out ON/OFF control with a control signal.  
     
     
         5 . The nonvolatile memory according to  claim 1 , further comprising: 
 an insulating film for capacitive coupling, which is provided on the floating gate electrode; and    a control gate electrode, which is provided on the insulating film for capacitive coupling.    
     
     
         6 . The nonvolatile memory according to  claim 1 , further comprising second conductivity-type source and drain regions, which are provided within the semiconductor substrate at both sides of the floating gate electrode, and which are separated from the first conductivity-type source and drain regions; 
 wherein two MISFETs of opposite conductivity type are configured with the regions between the two source and drain regions serving as channel regions; and    wherein the nonvolatile memory functions as a nonvolatile inverter.    
     
     
         7 . The nonvolatile memory according to  claim 6 , further comprising two insulating films for capacitive coupling, both provided above the floating gate electrode; and 
 control gate electrodes, each provided on an insulating film for capacitive coupling.    
     
     
         8 . The nonvolatile memory according to  claim 6 , further comprising a first-stage inverter for inputting complementary signals to the ferroelectric capacitor and the dielectric capacitor; 
 wherein the nonvolatile memory functions as a nonvolatile flip-flop.    
     
     
         9 . The nonvolatile memory according to  claim 8 , further comprising an intermediate inverter, which is disposed between the first-stage inverter and either the ferroelectric capacitor or the dielectric capacitors  
     
     
         10 . A method for driving a nonvolatile memory, the nonvolatile memory comprising: 
 a transistor having a source region, a drain region and a floating gate electrode;    a dielectric capacitor, which is connected to the floating gate electrode and has a dielectric layer;    a ferroelectric capacitor, which is connected to the floating gate electrode and has a ferroelectric layer; and    first and second polarization voltage application terminals, which are connected to the dielectric capacitor and the ferroelectric capacitor, respectively, and which apply voltage for generating polarization to the ferroelectric capacitor,    wherein the dielectric capacitor is composed of a polarization gate electrode connected by the floating gate electrode, the dielectric layer and the first polarization voltage application terminals,    wherein during writing, in accordance with the information “0” or “1” that is to be written, the voltage applied to the first and second polarization voltage application terminals is reversed between high and low.    
     
     
         11 . The method for driving a nonvolatile memory according to  claim 10 , wherein during read-out, a read-out voltage is applied to the first polarization voltage application terminal.