System and method for adjusting phase offsets

Abstract

Systems and methods that adjust phase offsets are provided. In one embodiment, a phase detector may include, for example, a delay block coupled to a first exclusive OR (XOR) gate via a first delay element; a first sequential device coupled the first XOR gate via a second delay element; a second sequential device coupled to the first sequential device and coupled to a second XOR gate via a third delay element; and a third sequential device coupled to the second sequential device and coupled to the second XOR gate via a fourth delay element.

What is claimed is:  
     
         1 . A phase detector, comprising: 
 a delay block coupled to a first exclusive OR (XOR) gate via a first delay element;    a first sequential device coupled the first XOR gate via a second delay element;    a second sequential device coupled to the first sequential device and coupled to a second XOR gate via a third delay element; and    a third sequential device coupled to the second sequential device and coupled to the second XOR gate via a fourth delay element.    
     
     
         2 . The phase detector according to  claim 1 , wherein the first delay element comprises a variable capacitor.  
     
     
         3 . The phase detector according to  claim 2 , wherein the variable capacitor comprises a transistor.  
     
     
         4 . The phase detector according to  claim 1 , wherein the first sequential device comprises a flip flop.  
     
     
         5 . The phase detector according to  claim 1 , wherein the second sequential device comprises a latch.  
     
     
         6 . The phase detector according to  claim 1 , wherein the third sequential device comprises a latch.  
     
     
         7 . The phase detector according to  claim 1 , wherein the delay block comprises a delay cell.  
     
     
         8 . The phase detector according to  claim 1 , wherein the delay block is adapted to incorporate a time delay that is approximately equal to the clock-to-output time delay of the first sequential device.  
     
     
         9 . The phase detector according to  claim 1 , wherein a clock signal with an adjustable frequency is coupled to the first sequential device and to the second sequential device.  
     
     
         10 . The phase detector according to  claim 9 , wherein an inverse of the clock signal with the adjustable frequency is coupled to the third sequential device.  
     
     
         11 . The phase detector according to  claim 1 , wherein a particular phase offset between a clock signal and a data signal may be locked by setting a particular time delay for the first delay element, the second delay element, the third delay element and the fourth delay element.  
     
     
         12 . The phase detector according to  claim 11 , wherein the particular time delay for each of the delay elements is different.  
     
     
         13 . The phase detector according to  claim 1 , wherein a locked phase relationship between a clock signal and a data signal is adjusted by adjusting a time delay in at least one of the first delay element, the second delay element, the third delay element and the fourth delay element.  
     
     
         14 . The phase detector according to  claim 1 , wherein the phase detector only adjusts a phase relationship between a clock signal and a data signal when the data signal is in transition.  
     
     
         15 . The phase detector according to  claim 1 , wherein an amount of phase offset locked in between the clock signal and the data signal is independent of data signal pattern.  
     
     
         16 . The phase detector according to  claim 1 , wherein the phase detector is part of a clock and data recovery circuit.  
     
     
         17 . The phase detector according to  claim 16 , wherein the clock and data recovery circuit does not charge or discharge current in its phase adjustment loop.  
     
     
         18 . The phase detector according to  claim 1 , wherein the first delay element comprises a programmable time delay.  
     
     
         19 . A system for adjusting a locked phase offset between a data signal and a clock signal, comprising: 
 a phase detector in which one or more data paths used in generating an error signal or a reference signal comprise a respective delay element;    a loop filter coupled to the phase detector; and    a voltage controlled oscillator coupled to the loop filter and an output of the voltage controlled oscillator coupled to an input of the phase detector.    
     
     
         20 . The system according to  claim 19 , wherein every data path used in generating the error signal or the reference signal comprises the respective delay element.  
     
     
         21 . A method for adjusting a locked phase offset between a data signal and a clock signal, comprising: 
 adjusting a time delay in a respective delay element disposed in each data path of a phase detector.    
     
     
         22 . The method according to  claim 21 , further comprising: 
 adjusting the locked phase offset between the data signal and the clock signal independent of data signal pattern.    
     
     
         23 . The method according to  claim 21 , further comprising: 
 adjusting phase relationship between the data signal and the clock signal only during a transition in the data signal.    
     
     
         24 . A method for adjusting a locked phase offset between a data signal and a clock signal, comprising: 
 adjusting a first time delay in a first data path of a phase detector; and    adjusting a second time delay in a second data path of the phase detector.