Semiconductor device, method of fabricating the same, and supttering apparatus

Abstract

A method of fabricating a semiconductor device comprises the steps of: (a) forming a mask layer over an upper surface of a semiconductor substrate such that the mask layer has an aperture penetrating the mask layer and having an inclined lateral wall so as to make the aperture inverted taper shaped; (b) forming a first dielectric layer at a first area over the upper surface of the semiconductor substrate within the aperture by sputtering at a first sputtering incidence direction; and (c) forming a first electrode layer at a second area over the upper surface of the semiconductor substrate within the aperture by sputtering at a second sputtering incidence direction which is different from the first sputtering incidence direction.

What is claimed is:  
     
         1 . A method of fabricating a semiconductor device comprising the steps of: 
 (a) forming a mask layer over an upper surface of a semiconductor substrate such that said mask layer has an aperture penetrating said mask layer and having an inclined lateral wall so as to make said aperture inverted taper shaped;    (b) forming a first dielectric layer at a first area over said upper surface of said semiconductor substrate within said aperture by sputtering at a first sputtering incidence direction; and    (c) forming a first electrode layer at a second area over said upper surface of said semiconductor substrate within said aperture by sputtering at a second sputtering incidence direction which is different from said first sputtering incidence direction.    
     
     
         2 . A method of  claim 1 , further comprising a step (d) of forming a metal electrode layer on said upper surface of said semiconductor substrate before said step (a).  
     
     
         3 . A method of  claim 2 , wherein said step (d) is conducted using an etching.  
     
     
         4 . A method of  claim 1 , further comprising a step (e) of forming a conductive area in said upper surface of said semiconductor substrate before said step (a).  
     
     
         5 . A method of  claim 4 , wherein said step (e) is conducted using an ion implantation.  
     
     
         6 . A method of  claim 4 , wherein said step (e) is conducted using an epitaxial growth.  
     
     
         7 . A method of  claim 1 , further comprising the steps of: 
 (f) forming a second dielectric layer at a third area over said upper surface of said semiconductor substrate within said aperture by sputtering at a third sputtering incidence direction; and    (g) forming a third electrode layer at a fourth area over said upper surface of said semiconductor substrate within said aperture by sputtering at a fourth sputtering incidence direction which is different from said first to third sputtering incidence directions.    
     
     
         8 . A method of  claim 7 , wherein said steps (b), (c), (f) and (g) are repeated in this order at desired times.  
     
     
         9 . A method of  claim 7 , wherein said first and third sputtering incidence directions are perpendicular to said upper surface of said semiconductor substrate.  
     
     
         10 . A method of  claim 7 , wherein an incident angle between said second sputtering incidence direction and a normal line perpendicular to said upper surface of said semiconductor substrate lies in a range of 10 degrees to 30 degrees, an incident angle between said fourth sputtering incidence direction and said normal line lies in a range of 10 degrees to 30 degrees, and said second sputtering incidence direction and said fourth sputtering incidence direction are opposite each other with respect to said normal line.  
     
     
         11 . A semiconductor device wherein a capacitor is formed on a chemical compound semiconductor substrate, wherein said capacitor comprising: 
 a first electrode layer;    a dielectric layer formed on said first electrode layer; and    a second electrode layer formed on said dielectric layer.    
     
     
         12 . A semiconductor device of  claim 11 , wherein said first electrode layer, said dielectric layer and said second electrode layer and said dielectric layer are placed on top of each other in this order.  
     
     
         13 . A semiconductor device of  claim 10 , wherein said capacitor has a function of removing a D.C. component current.  
     
     
         14 . A semiconductor device of  claim 10 , further comprising a first transistor and a second transistor each formed on said semiconductor substrate; 
 wherein one end of said first electrode layer is electrically connected to said first transistor, and one end of said second electrode layer is electrically connected to said second transistor.    
     
     
         15 . A semiconductor device of  claim 14 , wherein said one end of said first electrode layer is electrically connected to a source of said first transistor, and said one end of said second electrode layer is electrically connected to a gate of said second transistor.  
     
     
         16 . A semiconductor device of  claim 15 , wherein a ground potential is applied to said first electrode layer, and a negative potential is applied to said second electrode layer.  
     
     
         17 . A semiconductor device of  claim 10 , wherein: 
 said chemical compound semiconductor is a GaAs substrate; and    said dielectric layer is selected from the group consisting of a silicon nitride film, a tantalum oxide film, BST and STO.    
     
     
         18 . A semiconductor device of  claim 10 , wherein said electrode layer is a laminated layer including a layer of titanium and a layer of platinum.  
     
     
         19 . A sputtering apparatus comprising: 
 a sputtering chamber;    a wafer stage on which a wafer is set; and    a target stage on which a sputtering material is set;    said wafer stage and said target stage being installed in said sputtering chamber;    wherein said wafer stage comprises: 
 a fixed stage fixed to said sputtering chamber; and  
 a movable wafer holder holding said wafer and being free to rotate on said fixed stage, thereby making a sputtering incidence direction a desired direction.  
   
     
     
         20 . A sputtering apparatus of  claim 19 , wherein: 
 said fixed stage comprises a hemispherical depression on an upper surface thereof; and    said movable wafer holder has a projection of hemispherical shape which engages with said depression.    
     
     
         21 . A sputtering apparatus comprising: 
 a sputtering chamber;    a wafer stage on which a wafer is set; and    a plurality of target stages on which a sputtering material is set respectively;    said wafer stage and said target stages being installed in said sputtering chamber, and said target stages being disposed in positions at which sputtering incidence directions with respect to an upper surface of said wafer are mutually different;    wherein a sputtering material set on one of said target stages is deposited over said wafer by applying a high frequency voltage between said wafer stage and said one of said target stage, thereby depositing said sputtering material over said upper surface of said wafer.    
     
     
         22 . A multi-chamber type sputtering apparatus comprising a plurality of said sputtering chambers of  claim 19 .  
     
     
         23 . A multi-chamber type sputtering apparatus comprising a plurality of said sputtering chambers of  claim 21.