Apparatus and methods for wire load independent logic synthesis and timing closure with constant replacement delay cell libraries

Abstract

Disclosed is a method of generating an integrated circuit (IC) layout design. An initial layout netlist having a plurality of original cells is provided. A first original cell within the initial layout netlist is replaced with a first replacement cell having a different drive than the first original cell's drive but a same replacement delay as the first original cell when the first original cell is not optimal. The first replacement delay of a particular cell is the particular cell's total delay contribution to a particular delay path that includes the particular cell.

What is claimed is:  
     
         1 . A method of generating an integrated circuit (IC) layout design, the method comprising: 
 providing an initial layout netlist having a plurality of original cells; and    replacing a first original cell within the initial layout netlist with a first replacement cell having a different drive than the first original cell's drive but a same replacement delay as a first original delay of the first original cell when the first original cell is not optimal,    wherein the first replacement delay equals a total delay contribution to a particular delay path that includes the first replacement cell and the first original delay equals a total delay contribution to a particular delay path that includes the first original cell.    
     
     
         2 . A method as recited in  claim 1 , wherein the first replacement cell is taken from a constant replacement delay cell library having a plurality of cell families that each include a plurality of cells having different load capabilities and a same replacement delay.  
     
     
         3 . A method as recited in  claim 1 , wherein providing the initial layout netlist is accomplished by transforming a logic design netlist or logic design description into the layout netlist.  
     
     
         4 . A method as recited in  claim 1 , wherein the first replacement is prior to any routing procedure being performed on the layout netlist, wherein the first replacement cell is capable of driving the first original cell's load, excluding a wire load that is associated with the first original cell and is introduced by a subsequent routing procedure, the first original cell not being optimal when it is incapable of driving its own load, excluding the wire load.  
     
     
         5 . A method as recited in  claim 1 , wherein the first replacement is accomplished by ignoring a wire load for the first original cell and maximizing load slack associated with the first original cell.  
     
     
         6 . A method as recited in  claim 1 , wherein the first original cell is optimal when power consumption is optimized.  
     
     
         7 . A method as recited in  claim 2 , further comprising providing at least one family of the constant replacement delay cell library by: 
 selecting a maximum load for the family;    selecting a minimum load for the family;    selecting an incremental load for the family;    selecting a single replacement delay for the family which may vary for different signal paths through the cell, but remains constant across the family; and    generating a plurality of standard library cells to be included within the family, each cell having the selected replacement delay and a same logic function and being capable of driving different loads, wherein the loads associated with the family cells range from the selected minimum load through the selected maximum load in increments of the selected incremental load.    
     
     
         8 . A computer readable medium containing program instructions for generating an integrated circuit (IC) layout design, the computer readable medium comprising: 
 computer readable code for providing an initial layout netlist having a plurality of original cells;    computer readable code for replacing a first original cell within the initial layout netlist with a first replacement cell having a different drive than the first original cell's drive but a same replacement delay as a first original delay of the first original cell when the first original cell is not optimal, wherein the first replacement delay equals a total delay contribution to a particular delay path that includes the first replacement cell and the first original delay equals a total delay contribution to a particular delay path that includes the first original cell.; and    a computer readable medium for storing the computer readable codes.    
     
     
         9 . A computer readable medium as recited in  claim 8 , wherein the first replacement cell is taken from a constant replacement delay cell library having a plurality of cell families that each include a plurality of cells having different load capabilities and a same replacement delay.  
     
     
         10 . A computer readable medium as recited in  claim 8 , wherein providing the initial layout netlist is accomplished by transforming a logic design netlist or logic design description into the layout netlist.  
     
     
         11 . A computer readable medium as recited in  claim 8 , wherein the first replacement is prior to any routing procedure being performed on the layout netlist, wherein the first replacement cell is capable of driving the first original cell's load, excluding a wire load that is associated with the first original cell and is introduced by a subsequent routing procedure, the first original cell not being optimal when it is incapable of driving its own load, excluding the wire load.  
     
     
         12 . A computer readable medium as recited in  claim 8 , wherein the first replacement is accomplished by ignoring a wire load for the first original cell and maximizing load slack associated with the first original cell.  
     
     
         13 . A computer readable medium as recited in  claim 8 , wherein the first original cell is optimal when power consumption is optimized.  
     
     
         14 . A computer readable medium as recited in  claim 9 , the computer readable medium comprising: computer readable code for providing at least one family of the constant replacement delay cell library by: 
 selecting a maximum load for the family;    selecting a minimum load for the family;    selecting an incremental load for the family;    selecting a single replacement delay for the family which may vary for different signal paths through the cell, but remains constant across the family; and    generating a plurality of standard library cells to be included within the family, each cell having the selected replacement delay and a same logic function and being capable of driving different loads, wherein the loads associated with the family cells range from the selected minimum load through the selected maximum load in increments of the selected incremental load.    
     
     
         15 . A computer system operable to generate an integrated circuit (IC) layout design, the computer system comprising: 
 one or more processors;    one or more memory, wherein at least one of the processors and memory are adapted to: 
 provide an initial layout netlist having a plurality of original cells; and  
 replace a first original cell within the initial layout netlist with a first replacement cell having a different drive than the first original cell's drive but a same replacement delay as a first original delay of the first original cell when the first original cell is not optimal,  
 wherein the first replacement delay equals a total delay contribution to a particular delay path that includes the first replacement cell and the first original delay equals a total delay contribution to a particular delay path that includes the first original cell.  
   
     
     
         16 . A computer system as recited in  claim 15 , wherein the first replacement cell is taken from a constant replacement delay cell library having a plurality of cell families that each include a plurality of cells having different load capabilities and a same replacement delay.  
     
     
         17 . A computer system as recited in  claim 15 , wherein providing the initial layout netlist is accomplished by transforming a logic design netlist or logic design description into the layout netlist.  
     
     
         18 . A computer system as recited in  claim 15 , wherein the first replacement is prior to any routing procedure being performed on the layout netlist, wherein the first replacement cell is capable of driving the first original cell's load, excluding a wire load that is associated with the first original cell and is introduced by a subsequent routing procedure, the first original cell not being optimal when it is incapable of driving its own load, excluding the wire load.  
     
     
         19 . A computer system as recited in  claim 15 , wherein the first replacement is accomplished by ignoring a wire load for the first original cell and maximizing load slack associated with the first original cell.  
     
     
         20 . A computer system as recited in  claim 15 , wherein the first original cell is optimal when power consumption is optimized.  
     
     
         21 . A computer system as recited in  claim 16 , wherein at least one of the processors and memory are further adapted to provide at least one family of the constant replacement delay cell library by: 
 selecting a maximum load for the family;    selecting a minimum load for the family;    selecting an incremental load for the family;    selecting a single replacement delay for the family which may vary for different signal paths through the cell, but remains constant across the family; and    generating a plurality of standard library cells to be included within the family, each cell having the selected replacement delay and a same logic function and being capable of driving different loads, wherein the loads associated with the family cells range from the selected minimum load through the selected maximum load in increments of the selected incremental load.