Semiconductor integrated circuit device

Abstract

A gate electrode of MISFET Qs for information transmission in a memory cell-forming region is constituted of a built-up film of a polysilicon film and a W film, and gate electrodes of n channel-type MISFET Qn 1 and p channel-type MISFET's QP 1, Qp 2 in a peripheral circuit-forming region are each constituted of a built-up film of a polysilicon and a CoSi layer. The CoSi layer is formed on a source and a drain of these MISFET's, and any CoSi layer is not formed on a source and a drain of the MISFET for information transmission. As a result, refresh characteristics of a memory cell can be improved, and contact holes can be formed in high precision over the CoSi layer.

What is claimed is:  
     
         1 . A semiconductor integrated circuit device of the type which comprises a memory cell made of a MISFET for information transmission and a capacitor element and formed in a memory cell-forming region of a semiconductor substrate, and an n channel-type MISFET and a p channel-type MISFET formed in a peripheral circuit-forming region, said MISFET for information transmission, said n channel-type MISFET and said p channel-type MISFET, respectively, including a source and a drain formed in said semiconductor substrate, a gate insulating film formed on said semiconductor substrate between said source and said drain, and a gate electrode formed on said gate insulating film, wherein 
 (a) the gate electrode of said MISFET for information transmission has a metal layer, and    (b) the gate electrodes of said n channel-type MISFET and said p channel-type MISFET, respectively, have a first metal silicide layer, and a second metal silicide layer is formed on the source and the drain of said n channel-type MISFET and said p channel-type MISFET, respectively.    
     
     
         2 . A semiconductor integrated device according to  claim 1 , wherein any metal silicide layer is not formed on the source and the drain of said MISFET for information storage.  
     
     
         3 . A semiconductor integrated circuit device of the type which comprises a memory cell made of a MISFET for information transmission and a capacitor element and formed in a memory cell-forming region of a semiconductor substrate, and an n channel-type MISFET and a p channel-type MISFET formed in a peripheral circuit-forming region, said MISFET for information transmission, said n channel-type MISFET and said p channel-type MISFET, respectively, including a source and a drain formed in said semiconductor substrate, a gate insulating film formed on said semiconductor substrate between said source and said drain, and a gate electrode formed on said gate insulating film, wherein 
 (a) the gate electrode of said MISFET for information transmission is made of a built-up film of a silicon layer and a metal layer formed thereover, and    (b) the gate electrodes of said n channel-type MISFET and said p channel-type MISFET are, respectively, made of a silicon layer and a first metal silicide layer formed thereover, and a second metal silicide layer is formed on the source and the drain of said n channel-type MISFET and said p channel-type MISFET, respectively.    
     
     
         4 . A semiconductor integrated circuit device according to  claim 3 , wherein any metal suicide layer is not formed on the source and the drain of said MISFET for information transmission.  
     
     
         5 . A semiconductor integrated circuit device according to  claim 3 , wherein said metal layer is made of tungsten.  
     
     
         6 . A semiconductor integrated circuit device according to  claim 3 , wherein the first and second metal silicide layers are, respectively, made of a cobalt or titanium silicide layer.  
     
     
         7 . A semiconductor integrated circuit device according to  claim 3 , wherein the first and second metal silicide layers are layers formed at a contact between said metal layer and said silicon layer.  
     
     
         8 . A semiconductor integrated circuit device according to  claim 3 , further comprising an insulating layer formed on said n channel-type MISFET or said p channel-type MISFET, a first buried conductive layer formed in said insulating film over said gate electrode of said n channel-type MISFET or said p channel-type MISFET, and a second buried conductive layer in said insulating film over said source or said drain of said n channel-type MISFET or said p channel-type MISFET.  
     
     
         9 . A semiconductor integrated circuit device according to  claim 8 , wherein a portion over said n channel-type MISFET or said p channel-type MISFET is in a region surrounded by an isolation region, and the first buried conductive layer or the second buried conductive layer extends over said isolation region.  
     
     
         10 . A semiconductor integrated circuit device according to  claim 3 , further comprising first and second insulating films formed over said MISFET for information transmission, and an insulating film formed over said n channel-type MISFET and said p channel-type MISFET at the same level as said second insulating film.  
     
     
         11 . A semiconductor integrated circuit device according to  claim 8 , further comprising a first, second and third insulating films formed over said MISFET for information transmission, and a double-layered insulating film formed over said n channel-type MISFET and said p channel-type MISFET at the same levels as said second and third insulating layers, respectively, wherein said first and second buried conductive layers are, respectively, formed in said double-layered insulating film formed over said n channel-type MISFET and said p channel-type MISFET.  
     
     
         12 . A semiconductor integrated circuit device of the type which comprises a memory cell made of a MISFET for information transmission and a capacitor element and formed in a memory cell-forming region of a semiconductor substrate, and an SRAM memory cell having an n channel-type MISFET and a p channel-type MISFET formed in a peripheral circuit-forming region, said MISFET for information transmission, said n channel-type MISFET and said p channel-type MISFET, respectively, including a source and a drain formed in said semiconductor substrate, a gate insulating film formed on said semiconductor substrate between said source and said drain, and a gate electrode formed on said gate insulating film, wherein 
 (a) the gate electrode of said MISFET for information transmission is made of a built-up film of a silicon layer and a metal layer, and    (b) the gate electrodes of said n channel-type MISFET and said p channel-type MISFET are, respectively, made of a silicon layer and a first metal silicide layer formed thereover, and a second metal silicide layer is formed on the source and the drain of said n channel-type MISFET and said p channel-type MISFET, respectively.    
     
     
         13 . A semiconductor integrated circuit device according to  claim 12 , wherein a metal silicide layer is not formed on the source and the drain of said MISFET for information transmission.  
     
     
         14 . A semiconductor integrated circuit device according to  claim 12 , wherein said metal layer is made of tungsten.  
     
     
         15 . A semiconductor integrated circuit device according to  claim 12 , wherein the first and second metal silicide layers are, respectively, made of a cobalt or titanium silicide layer.  
     
     
         16 . A semiconductor integrated circuit device according to  claim 12 , wherein the first and second metal silicide layers are, respectively, made of a layer formed at a contact between the metal layer and the silicon layer.  
     
     
         17 . A semiconductor integrated circuit device according to  claim 12 , wherein the gate electrode of said p channel-type MISFET and the source or drain of said n channel-type MISFET are connected with a buried conductive layer, and said buried conductive film is formed in an insulating film on said n-channel-type MISFET or said p channel-type MISFET.  
     
     
         18 . A semiconductor integrated circuit device according to  claim 12 , wherein the gate electrode of said n channel-type MISFET and the source or drain of said p channel-type MISFET are connected with a buried conductive layer, and said buried conductive film is formed in an insulating film on said n-channel-type MISFET or said p channel-type MISFET.