Array substrate, method of inspecting array substrate, and liquid crystal display

Abstract

An array substrate is provided for which an OS inspection can be performed without increasing the area of a signal driving circuit formed on the array substrate, and for which the manufacturing cost can be reduced. The array substrate includes a substrate, scanning lines, signal lines, pixel electrodes connected via switching elements provided at the intersections of the scanning lines and the signal lines, a plurality of input/output terminals provided at an edge portion of the substrate, a scanning line driving circuit, a signal line driving circuit for supplying picture signals sent from the outside to one ends of the signal lines via the input/output terminals, and a wiring line commonly connecting the other ends of the signal lines to at least one of the input/output terminals. A predetermined level of voltage is applied between the input/output terminal to which the wiring line is connected and another input/output terminal which at least supplies picture signals, and a current flowing at that time is measured to detect failures.

What is claimed is:  
     
         1 . An array substrate comprising: 
 a substrate;    a plurality of scanning lines formed on the substrate;    a plurality of signal lines formed on the substrate so as to intersect the scanning lines, each signal line having one end and the other end;    thin film transistors provided at intersections of the scanning lines and the signal lines, a gate of each thin film transistor being connected to the corresponding scanning line, and a source thereof being connected to the corresponding signal line;    pixel electrodes each corresponding to one of the thin film transistors, and each being connected to a drain of the corresponding thin film transistor;    an input/output terminal group provided at an edge portion of the substrate, including input/output terminals used for inputting signals from the outside and outputting signals to the outside;    a scanning line driving circuit for driving the scanning lines;    a signal line driving circuit, connected to the one end of each signal line, for driving the signal lines; and    a first wiring line formed on the substrate, for commonly connecting the other ends of the signal lines to at least one of the input/output terminals in the input/output terminal group.    
     
     
         2 . The array substrate according to  claim 1 , further including: 
 storage capacitors each corresponding to one of the pixel electrodes and one end of each being connected to the corresponding pixel electrode; and    storage capacitor lines each connected to the other end of each storage capacitor, wherein the storage capacitor lines are commonly connected to one of the input/output terminals in the input/output terminal group.    
     
     
         3 . The array substrate according to  claim 2 , wherein the other end of each signal line is connected to the first wiring line via a resistor.  
     
     
         4 . The array substrate according to  claim 2 , wherein the other end of each signal line is connected to the first wiring line via a switching element which can be turned on/of f from the outside.  
     
     
         5 . The array substrate according to  claim 2 , wherein the other end of each signal line is connected to the first wiring line via a diode.  
     
     
         6 . The array substrate according to  claim 5  wherein the first wiring line includes a second wiring line and a third wiring line connected to the different input/output terminals, and a first diode and a second diode are provided to the other end of each signal line, an anode of the first diode being connected to the other end of the signal line, a cathode thereof being connected to the second wiring line, an anode of the second diode being connected to the third wiring line, and a cathode thereof being connected to the other end of the signal line.  
     
     
         7 . The array substrate according to  claim 6 , wherein the second wiring line and the third wiring line are also used as lines for input/output signals of the scanning line driving circuit or the signal line driving circuit.  
     
     
         8 . The array substrate according to  claim 1 , further including a video bus connected to at least one of the input/output terminals of the input/output terminal group, wherein the signal line driving circuit includes selecting switches each corresponding to a signal line, one end of each selecting switch being connected to the corresponding signal line, and the other end thereof being connected to the video bus.  
     
     
         9 . The array substrate according to  claim 8 , further including: 
 storage capacitors each corresponding to one of the pixel electrodes, and one end of each being connected to the corresponding pixel electrode; and    storage capacitor lines each connected to the other end of each storage capacitor,    wherein the storage capacitor lines are commonly connected to one of the input/output terminals in the input/output terminal group.    
     
     
         10 . The array substrate according to  claim 9 , wherein the other end of each signal line is connected to the first wiring line via a resistor.  
     
     
         11 . The array substrate according to  claim 9 , wherein the other end of each signal line is connected the first wiring line via a switching element which can be turned on/off from the outside.  
     
     
         12 . The array substrate according to  claim 9 , wherein the other end of each signal line is connected to the first wiring line via a diode.  
     
     
         13 . The array substrate according to  claim 12  wherein the first wiring line includes a second wiring line and a third wiring line connected to different input/output terminals, and a first diode and a second diode are provided to each signal line, an anode of the first diode being connected to the other end of the signal line, a cathode thereof being connected to the second wiring line, an anode of the second diode being connected to the third wiring line, and a cathode thereof being connected to the other end of the signal line.  
     
     
         14 . The array substrate according to  claim 8 , wherein the other ends of the selecting switches, one ends of which are connected to the (2 k−1)-th signal line and the (2K)-th signal line, counted from one side, where k is a natural number, are commonly connected to the video bus.  
     
     
         15 . The array substrate according to  claim 8 , wherein: 
 the first wiring line includes second to fifth wiring lines connected to the different input/output terminals;    a first diode and a second diode are provided to the other end of each signal line, an anode of the first diode being connected to the other end of the signal line, and a cathode of the second diode being connected to the other end of the signal line;    the signal lines are divided into at least a first and a second signal line groups;    a cathode of the first diode, the anode of which is connected to the other end of the signal line included in the first signal line group, is connected to the second wiring line;    an anode of the second diode, the cathode of which is connected to the other end of the signal line included in the second signal line group is connected to the third wiring line;    a cathode of the first diode, the anode of which is connected to the other end of the signal line included in the second signal line group is connected to the fourth wiring line; and    an anode of the second diode, the cathode of which is connected to the other end of the signal line included in the second signal line group is connected to the fifth wiring line.    
     
     
         16 . The array substrate according to  claim 15 , wherein the first signal line group includes odd-numbered signal lines counted from one side, and the second signal line group includes even-numbered signal lines counted from the one side.  
     
     
         17 . The array substrate according to  claim 16 , wherein the other ends of the selecting switches, one ends of which are connected to the (2 k−1)-th signal line and the (2K)-th signal line, counted from one end, where k is a natural number, are commonly connected to the video bus.  
     
     
         18 . A liquid crystal display comprising: 
 the array substrate according to  claim 1;     an opposite substrate formed on a second substrate, including a common electrode;    a liquid crystal layer provided between the array substrate and the opposite substrate.    
     
     
         19 . A method of inspecting the array substrate according to  claim 1 , comprising: 
 applying a predetermined level of voltage between the input/output terminal to which the first wiring line is connected and another input/output terminal which at least supplies picture signals; and    measuring a current flowing through the input/output terminals to which the predetermined level of voltage is applied.    
     
     
         20 . A method of inspecting the array substrate according to  claim 2 , comprising: 
 applying a predetermined level of voltage between the input/output terminal to which the first wiring line is connected and another input/output terminal which at least supplies picture signals, and applying a potential different from the potential of the input/output terminal which at least supplies picture signals to the scanning line or the storage capacitor line; and    measuring a current flowing through the input/output terminals to which the predetermined level of voltage is applied.