Semiconductor memory cell, method for fabricating the memory cell, and semiconductor memory device

Abstract

In order to be able to store information in a non-volatile fashion as compactly and as flexibly as possible in a semiconductor memory cell, the original gate region of a conventional memory transistor is removed, and a memory gate configuration having a plurality of memory gates that are spatially separate from one another and that are electrically insulated with respect to one another is formed.

I claim:  
     
         1 . A semiconductor memory cell for non-volatile information storage, comprising: 
 a memory gate configuration designed for non-volatile information storage;    a source/drain configuration designed for accessing said memory gate configuration; and    a control gate configuration designed for controlling access to said memory gate configuration;    said memory gate configuration having a plurality of memory gate regions; and    each of said plurality of said memory gate regions being designed for essentially independent information storage such that a corresponding plurality of information units can be stored independently of one another.    
     
     
         2 . The semiconductor memory cell according to  claim 1 , wherein the plurality of the information units are binary bits.  
     
     
         3 . The semiconductor memory cell according to  claim 1 , wherein said plurality of said memory gate regions are pairwise, spatially separate from one another.  
     
     
         4 . The semiconductor memory cell according to  claim 3 , wherein said plurality of said memory gate regions are electrically insulated from one another.  
     
     
         5 . The semiconductor memory cell according to  claim 1 , wherein said plurality of said memory-gate regions are electrically insulated from one another.  
     
     
         6 . The semiconductor memory cell according to  claim 1 , wherein: 
 said control gate configuration has a common control gate; and    access to said plurality of said memory gate regions is jointly controllable by said common control gate.    
     
     
         7 . The semiconductor memory cell according to  claim 1 , wherein: 
 said source/drain configuration includes a plurality of source/drain regions present in a number corresponding to a number of said plurality of said memory gate regions; and    a respective one of said plurality of said source/drain regions is assigned to a respective one of said plurality of said memory gate regions such that said respective one of said plurality of said memory gate regions can be accessed using said control gate configuration and said respective one of said plurality of said source/drain regions.    
     
     
         8 . The semiconductor memory cell according to  claim 1 , wherein said plurality of said memory gate regions have essentially identical geometrical properties.  
     
     
         9 . The semiconductor memory cell according to  claim 8 , wherein said plurality of said memory gate regions have essentially identical material properties.  
     
     
         10 . The semiconductor memory cell according to  claim 1 , wherein said plurality of said memory gate regions have essentially identical material properties.  
     
     
         11 . The semiconductor memory cell according to  claim 1 , wherein: 
 said control gate configuration has a control gate and said source/drain configuration has a plurality of source/drain regions; and    said plurality of said memory gate regions are configured and designed to be essentially electrically insulated from one another, from said control gate and from said plurality of said source/drain regions.    
     
     
         12 . The semiconductor memory cell according to  claim 1 , wherein said plurality of said memory gate regions are designed as floating gate regions so that the semiconductor memory cell functions as a floating gate memory cell.  
     
     
         13 . The semiconductor memory cell according to  claim 1 , wherein said plurality of said memory gate regions are designed and configured as essentially capacitively coupled floating gates.  
     
     
         14 . The semiconductor memory cell according to  claim 13 , wherein said floating gates are made of a material selected from a group consisting of a polysilicon material, a polycide, and a metal.  
     
     
         15 . The semiconductor memory cell according to  claim 1 , wherein said plurality of said memory gate regions are floating gates made of a material selected from a group consisting of a polysilicon material, a polycide, and a metal.  
     
     
         16 . The semiconductor memory cell according to  claim 1 , wherein: said plurality of said memory gate regions are designed as charge trapping gates so that the semiconductor memory cell functions as a charge trapping memory cell.  
     
     
         17 . The semiconductor memory cell according to  claim 16 , wherein said charge trapping gates include a material in which charge trapping states can be formed.  
     
     
         18 . The semiconductor memory cell according to  claim 17 , wherein said material of said charge trapping gates is an insulator having a sufficient number of defects capable of being occupied by electrons and/or holes.  
     
     
         19 . The semiconductor memory cell according to  claim 17 , wherein: said material of said charge trapping gates is an insulator in which a sufficient number of defects can be formed; and said defects can be occupied by electrons and/or holes.  
     
     
         20 . The semiconductor memory cell according to  claim 17 , comprising: 
 a channel region; and    an insulation region made of silicon dioxide;    said source/drain configuration having a plurality of source/drain regions;    said control gate configuration having a control gate;    said insulating region configured for insulating said charge trapping gates from said control gate, said plurality of said source/drain regions and said channel region;    said charge trapping gates being composed of silicon nitride;    said charge trapping gates having a structure selected from a group consisting of an ONO structure and an NO structure; and    said charge trapping gates including a material selected from a group consisting of ZrO 2 , Al 2 O 3 , Ta 2 O 5 , HfO 2 .    
     
     
         21 . The semiconductor memory cell according to  claim 1 , wherein each one of said plurality of said memory gate regions can assume a plurality of charge or potential states corresponding to information states assigned to said plurality of said memory gate regions.  
     
     
         22 . The semiconductor memory cell according to  claim 1 , wherein: 
 said source/drain configuration includes a plurality of source/drain regions;    said control gate configuration includes a control gate configured and designed to be essentially electrically insulated from said plurality of said memory gate regions and from said plurality of said source/drain regions.    
     
     
         23 . The semiconductor memory cell according to  claim 1 , wherein said control gate configuration includes a control gate composed of a material selected from a group consisting of a polysilicon material, a polycide, and a metal.  
     
     
         24 . The semiconductor memory cell according to  claim 1 , comprising: 
 an intermediate insulation region;    said control gate configuration including a control gate;    said plurality of said memory gate regions being pairwise, spatially separate from one another;    said plurality of said memory gate regions and said control gate being configured in direct spatial proximity to one another; and    said intermediate insulation region located between said control gate and said plurality of said memory gate regions.    
     
     
         25 . The semiconductor memory cell according to  claim 24 , wherein said intermediate insulation region is an intermediate dielectric.  
     
     
         26 . The semiconductor memory cell according to  claim 1 , comprising: 
 an insulation region;    said source/drain configuration including a plurality of source/drain regions;    each one of said plurality of said memory gate regions being designed and configured in direct spatial proximity to a respective one of said plurality of said source/drain regions such that a spatial overlap is formed between said one plurality of said memory gate regions and said respective one of said plurality of said source/drain regions; and    said insulation region provided between said one plurality of said memory gate regions and said respective one of said plurality of said source/drain regions.    
     
     
         27 . The semiconductor memory cell according to  claim 26 , wherein said insulation region is formed from a silicon dioxide material.  
     
     
         28 . The semiconductor memory cell according to  claim 1 , comprising: 
 an insulation region formed with a recess;    said plurality of said memory gate regions designed as spacer, elements embedded in said recess of said insulation region.    
     
     
         29 . The semiconductor memory cell according to  claim 1 , wherein said plurality of said memory gate regions are designed as exchange elements for at least a part of an original gate of a conventional MOSFET.  
     
     
         30 . The semiconductor memory cell according to  claim 29 , comprising: 
 an additional insulator, said plurality of said memory gate regions defining a level; and    an intermediate region located between said plurality of said memory gate regions being filled with said additional insulator to at most the level of said plurality of said memory gate regions to form an insulator thickness greater than a thickness of an original gate oxide or tunnel oxide.    
     
     
         31 . A semiconductor memory device, comprising: 
 a plurality of memory cells designed for non-volatile information storage;    each one of said plurality of said memory cells including: 
 a memory gate configuration designed for non-volatile information storage;  
 a source/drain configuration designed for accessing said memory gate configuration; and  
 a control gate configuration designed for controlling access to said memory gate configuration;  
 said memory gate configuration having a plurality of memory gate regions; and  
 each of said plurality of said memory gate regions being designed for essentially independent information storage such that a corresponding plurality of information units can be stored independently of one another.  
   
     
     
         32 . The semiconductor memory device according to  claim 31 , wherein: 
 said control gate configuration of each one of said plurality of said memory cells includes a control gate; and    said control gate of adjacent ones of at least some of said plurality of said memory cells are designed as a common control gate.    
     
     
         33 . A method for fabricating a semiconductor memory cell for non-volatile information storage, the method which comprises: 
 providing a memory gate configuration having a plurality of memory gate regions in which each one of the plurality of the memory gate regions is designed for essentially independently storing information such that a corresponding plurality of information units can be stored independently of one another;    providing a source/drain configuration designed for accessing the memory gate configuration; and    providing a control gate configuration for controlling access to the memory gate configuration.    
     
     
         34 . The method according to  claim 33 , wherein the information units are binary bits.  
     
     
         35 . The method according to  claim 33 , which comprises designing the plurality of the memory gate regions to be pairwise, spatially separate from one another.  
     
     
         36 . The method according to  claim 33 , which comprises designing the plurality of the memory gate regions to be electrically insulated from one another.  
     
     
         37 . The method according to  claim 33 , which comprises providing the control gate configuration with a common control gate for jointly controlling access to the plurality of the memory gate regions.  
     
     
         38 . The method according to  claim 33 , which comprises: 
 providing the source/drain configuration with a plurality of source/drain regions present in a number corresponding to a number of the plurality of the memory gate regions; and    assigning each one of the plurality of the source/drain regions to a respective one of the plurality of the memory gate regions such that the one of the plurality of the memory gate regions can be accessed using the control gate configuration and the one of the plurality of the source/drain regions.    
     
     
         39 . The method according to  claim 33 , which comprises designing the plurality of the memory gate regions to have essentially identical geometrical properties.  
     
     
         40 . The method according to  claim 33 , which comprises designing the plurality of the memory gate regions to have essentially identical material properties.  
     
     
         41 . The method according to  claim 33 , which comprises 
 providing the control gate configuration with a control gate and providing the source/drain configuration with a plurality of source/drain regions; and    configuring and designing the plurality of the memory gate regions to be essentially electrically insulated from one another, from the control gate and from the plurality of the source/drain regions.    
     
     
         42 . The method according to  claim 33 , which comprises designing the plurality of the memory gate regions as floating gate regions or floating gates so that the semiconductor memory cell functions as a floating gate memory cell.  
     
     
         43 . The method according to  claim 42 , which comprises designing and configuring the plurality of the memory gate regions as floating gates being essentially capacitively coupled.  
     
     
         44 . The method according to  claim 33 , which comprises designing the plurality of the memory gate regions as floating gates made of a material selected from a group consisting of a polysilicon material, a polycide, and a metal.  
     
     
         45 . The method according to  claim 33 , which comprises designing the plurality of the memory gate regions as charge trapping gate regions or charge trapping gates so that the semiconductor memory cell functions as a charge trapping memory cell.  
     
     
         46 . The method according to  claim 45 , which comprises: designing the plurality of the memory gate regions as charge trapping gates formed with silicon nitride; 
 providing the plurality of the memory gate regions with an ONO structure or an NO structure;    providing the plurality of the memory gate regions with a material selected from a group consisting of ZrO 2 , Al 2 O 3 , Ta 2 O 5 , and HfO 2 ; and    providing an insulation region between the charge trapping gates and a control gate of the control gate configuration.    
     
     
         47 . The method according to  claim 46 , which comprises also providing the insulation region between the charge trapping gates and source/drain regions of the source/drain configuration and between the charge trapping gates and a channel region.  
     
     
         48 . The method according to  claim 33 , which comprises: designing the plurality of the memory gate regions as charge trapping gates so that the semiconductor memory cell functions as a charge trapping memory cell; and 
 forming the charge trapping gates using a material in which charge trapping states can be formed.    
     
     
         49 . The method according to  claim 48 , which comprises: providing the material of the charge trapping gates as an insulator that has or that can form a sufficient number of defects that can be occupied by electrons and/or holes.  
     
     
         50 . The method according to  claim 33 , which comprises designing the plurality of the memory gate regions such that a plurality of charge and/or potential states can be assumed which correspond to information states assigned to the plurality of the memory gate regions.  
     
     
         51 . The method according to  claim 50 , wherein the plurality of the charge and/or potential states is exactly two states.  
     
     
         52 . The method according to  claim 33 , which comprises providing the control gate configuration with a control gate that is electrically insulated from the plurality of the memory gate regions and from source/drain regions of the source/drain configuration.  
     
     
         53 . The method according to  claim 33 , which comprises providing the control gate configuration with a control gate formed from a material selected from a group consisting of a polysilicon material, a polycide, and a metal.  
     
     
         54 . The method according to  claim 33 , which comprises: 
 providing the control gate configuration with a control gate;    configuring the plurality of the memory gate regions and the control gate in direct spatial proximity to one another; and    providing an intermediate insulation region between the control gate and the plurality of the memory gate regions.    
     
     
         55 . The method according to  claim 54 , which comprises providing the intermediate insulation region as an intermediate dielectric.  
     
     
         56 . The method according to  claim 33 , which comprises: 
 configuring each one of said plurality of said memory gate regions in direct spatial proximity to an assigned source/drain region such that a spatial overlap is formed between the one of said plurality of said memory gate regions and the assigned source/drain region; and    providing an insulation region between one of said plurality of said memory gate regions and the assigned source/drain region.    
     
     
         57 . The method according to  claim 56 , which comprises forming the insulation region from silicon dioxide.  
     
     
         58 . The method according to  claim 33 , which comprises designing the plurality of the memory gate regions as spacer elements embedded in a recess of an insulation region.  
     
     
         59 . The method according to  claim 33 , which comprises designing the plurality of the memory gate regions to replace at least a part of an original gate of a conventional MOSFET.  
     
     
         60 . The method according to  claim 33 , which comprises: 
 first, using self-aligning polysilicon technology to form a conventional MOSFET having an original gate embedded in an insulation region;    second, removing the original gate of the MOSFET to create a recess in the insulation region embedding the original gate; and    third, forming the plurality of the memory gate regions in the recess, embedding the plurality of the memory gate regions in an insulating manner, and providing the control gate configuration.    
     
     
         61 . The method according to  claim 33 , which comprises: first embedding an original gate of a conventional MOSFET in an insulation region, the original gate having a surface region defining a level; and second, performing a planarization step and stopping on the level of the surface region of the original gate.  
     
     
         62 . The method according to  claim 61 , which comprises providing the insulation region as SiO 2 .  
     
     
         63 . The method according to  claim 61 , which comprises using a masked etching to remove the original gate of the conventional MOSFET and to thereby form a recess in the insulation region in a region above and between source/drain regions of the source/drain configuration.  
     
     
         64 . The method according to  claim 63 , which comprises conformally depositing a spacer layer such that the recess is lined.  
     
     
         65 . The method according to  claim 64 , which comprises providing the spacer layer as silicon nitride, an ONO structure, or an NO structure.  
     
     
         66 . The method according to  claim 63 , which comprises conformally depositing at least one material layer for producing the plurality of the memory gate regions such that edge regions of the recess are lined.  
     
     
         67 . The method according to  claim 66 , which comprises: 
 in order to form floating gates, using an electrically conductive material for the material layer for producing the plurality of the memory gate regions;    for forming charge trapping gates, using an electrically insulating material for the material layer for producing the plurality of the memory gate regions; and    for the electrically insulating material, using a material that has or that can form a high density of traps.    
     
     
         68 . The method according to  claim 66 , which comprises patterning the material layer by anisotropically etching the material layer such that the plurality of the memory gate regions remain as spatially separate parts of the material layer in edge regions of the recess.  
     
     
         69 . The method according to  claim 68 , which comprises performing a thermal oxidation or a deposition and subsequently etching back to make an original gate insulator or an original gate oxide located between the plurality of the memory gate regions thicker than a gate insulator or a gate oxide located below the plurality of the memory gate regions.  
     
     
         70 . The method according to  claim 68 , which comprises conformally depositing at least one insulation layer to embed the plurality of the memory gate-regions in the insulation layer.  
     
     
         71 . The method according to  claim 70 , which comprises depositing and patterning at least one material layer for the control gate configuration such that the recess is filled.