Non-volatile semiconductor memory device and manufacturing method thereof

Abstract

The non-volatile semiconductor memory device has a booster including a capacitor, and a storage circuit including a storage element. The capacitor has a lower electrode, a capacitor capacitance insulating film and an upper electrode. The lower electrode of the capacitor is shaped to have an increased surface area.

What is claimed is:  
     
         1 . A non-volatile semiconductor memory device, comprising: 
 a booster including a capacitor having a lower electrode, a capacitor capacitance insulating film and an upper electrode; and    a storage element, wherein 
 the lower electrode is shaped to have an increased surface area.  
   
     
     
         2 . The non-volatile semiconductor memory device according to  claim 1 , wherein the lower electrode has a plurality of holes.  
     
     
         3 . The non-volatile semiconductor memory device according to  claim 1 , wherein the lower electrode is formed by a plurality of island-shaped lower electrode portions.  
     
     
         4 . The non-volatile semiconductor memory device according to  claim 1 , wherein the lower electrode is formed by a plurality of stripe-shaped lower electrode portions.  
     
     
         5 . The non-volatile semiconductor memory device according to  claim 4 , wherein a distance S between the lower electrode portions and a thickness T of the lower electrode portions have a relation of S<2T.  
     
     
         6 . The non-volatile semiconductor memory device according to  claim 1 , wherein a voltage V 1  which is applied to the upper electrode and a voltage V 2  which is applied to the lower electrode have a relation of V 1 <V 2 .  
     
     
         7 . The non-volatile semiconductor memory device according to  claim 1 , wherein the lower electrode has a plurality of concavities.  
     
     
         8 . The non-volatile semiconductor memory device according to  claim 1 , wherein the lower electrode has a plurality of convexities.  
     
     
         9 . The non-volatile semiconductor memory device according to  claim 1 , wherein the lower electrode has a plurality of stripe-shaped convexities.  
     
     
         10 . The non-volatile semiconductor memory device according to  claim 1 , wherein 
 the storage element has a tunnel insulating film, a floating gate electrode, a storage element capacitance insulating film and a control gate electrode,    the floating gate electrode and the lower electrode are formed from a conductive film which is formed in a same step,    the storage element capacitance insulating film and the capacitor capacitance insulating film are formed from an insulating film which is formed in a same step, and    the control gate electrode and the upper electrode are formed from a conductive film which is formed in a same step.    
     
     
         11 . A method for manufacturing a non-volatile semiconductor memory device, comprising: 
 a first step of forming an element isolation insulating film in a semiconductor substrate in order to define a storage circuit region and a capacitor region;    a second step of forming a plate-like conductive film in the capacitor region and etching the plate-like conductive film to form a lower electrode having an increased surface area;    a third step of forming a capacitor capacitance insulating film and an upper electrode on the lower electrode; and    a fourth step of forming in the storage circuit region a storage element having a tunnel insulating film, a floating gate electrode, a storage element capacitance insulating film and a control gate electrode.    
     
     
         12 . The method according to  claim 11 , wherein the lower electrode is formed into a plurality of holes, a plurality of island-shaped lower electrode portions, or a plurality of stripe-shaped lower electrode portions by etching a whole thickness of the conductive film in the second step.  
     
     
         13 . The method according to  claim 11 , wherein the lower electrode is formed into a plurality of concavities, a plurality of convexities, or a plurality of stripe-shaped convexities by etching only an upper portion of the conductive film in the second step.  
     
     
         14 . The method according to  claim 11 , wherein 
 the floating gate electrode and the lower electrode are formed from a conductive film which is formed in a same step,    the storage element capacitance insulating film and the capacitor capacitance insulating film are formed from an insulating film which is formed in a same step, and    the control gate electrode and the upper electrode are formed from a conductive film which is formed in a same step.    
     
     
         15 . A method for manufacturing a non-volatile semiconductor memory device, comprising: 
 a first step of forming an element isolation insulating film in a semiconductor substrate in order to define a storage circuit region, a logic circuit region and a capacitor region;    a second step of sequentially forming a first insulating film and a first conductive film on the semiconductor substrate and removing the first conductive film in the logic circuit region;    a third step of etching the first conductive film in the capacitor region to form a lower electrode having an increased surface area;    a fourth step of removing the first insulating film in the logic circuit region and an exposed portion of the first insulating film in the capacitor region and forming a second insulating film on the first conductive film in the storage circuit region, the semiconductor substrate in the logic circuit region, and the lower electrode in the capacitor region;    a fifth step of removing the second insulating film in the logic circuit region and sequentially forming a third insulating film and a second conductive film on the second insulating film in the storage circuit region and the capacitor region and on the semiconductor substrate in the logic circuit region;    a sixth step of forming in the storage circuit region a tunnel insulating film from the first insulating film, a floating gate electrode from the first conductive film, a storage element capacitance insulating film from the second and third insulating films, and a control gate electrode from the second conductive film;    a seventh step of forming in the logic circuit region a gate insulating film from the third insulating film and a gate electrode from the second conductive film; and    an eighth step of forming in the capacitor region a capacitor capacitance insulating film from the second and third insulating films and an upper electrode from the second conductive film.    
     
     
         16 . The method according to  claim 15 , wherein the lower electrode is formed into a plurality of holes, a plurality of island-shaped lower electrode portions, or a plurality of stripe-shaped lower electrode portions by etching a whole thickness of the first conductive film in the third step.  
     
     
         17 . The method according to  claim 15 , wherein the lower electrode is formed into a plurality of concavities, a plurality of convexities, or a plurality of stripe-shaped convexities by etching only an upper portion of the first conductive film in the third step.  
     
     
         18 . A method for manufacturing a non-volatile semiconductor memory device, comprising: 
 a first step of forming an element isolation insulating film in a semiconductor substrate in order to define a storage circuit region, a logic circuit region and a capacitor region;    a second step of sequentially forming a first insulating film and a first conductive film on the semiconductor substrate;    a third step of etching the first conductive film in the capacitor region to form a lower electrode having an increased surface area;    a fourth step of forming a second insulating film on the first conductive film in the storage circuit region and the logic circuit region and on the lower electrode in the capacitor region;    a fifth step of removing the first insulating film, the first conductive film and the second insulating film in the logic circuit region and sequentially forming a third insulating film and a second conductive film on the second insulating film in the storage circuit region and the capacitor region and on the semiconductor substrate in the logic circuit region;    a sixth step of forming in the storage circuit region a tunnel insulating film from the first insulating film, a floating gate electrode from the first conductive film, a storage element capacitance insulating film from the second and third insulating films, and a control gate electrode from the second conductive film;    a seventh step of forming in the logic circuit region a gate insulating film from the third insulating film and a gate electrode from the second conductive film; and    an eighth step of forming in the capacitor region a capacitor capacitance insulating film from the second and third insulating films and an upper electrode from the second conductive film.    
     
     
         19 . The method according to  claim 18 , wherein the lower electrode is formed into a plurality of holes, a plurality of island-shaped lower electrode portions, or a plurality of stripe-shaped lower electrode portions by etching a whole thickness of the conductive film in the third step.  
     
     
         20 . The method according to  claim 18 , wherein the lower electrode is formed into a plurality of concavities, a plurality of convexities, or a plurality of stripe-shaped convexities by etching only an upper portion of the conductive film in the third step.  
     
     
         21 . The non-volatile semiconductor memory device according to  claim 1 , wherein 
 the storage element has a charge storage film and a gate electrode,    the charge storage film and the capacitor capacitance insulating film are formed from an insulating film which is formed in a same step, and    the gate electrode and the upper electrode are formed from a conductive film which is formed in a same step.    
     
     
         22 . A method for manufacturing a non-volatile semiconductor memory device, comprising: 
 a first step of forming an element isolation insulating film in a semiconductor substrate in order to define a storage circuit region and a capacitor region;    a second step of forming a concavity in a semiconductor substrate included in the capacitor region, and implanting impurities into the concavity to form a lower electrode;    a third step of sequentially forming an insulating film and a conductive film on the semiconductor substrate including the lower electrode;    a fourth step of forming in the storage circuit region a charge storage film from the insulating film and a first gate electrode from the conductive film; and    a fifth step of forming in the capacitor region a capacitor capacitance insulating film from the insulating film and an upper electrode from the conductive film.    
     
     
         23 . The method according to  claim 22 , wherein, in the third step, the insulating film is formed by depositing a silicon oxide film on the semiconductor substrate and nitriding an upper portion of the deposited silicon oxide film.  
     
     
         24 . The method according to  claim 22 , wherein, in the third step, the insulating film is formed by sequentially depositing a silicon oxide film and a silicon nitride film on the semiconductor substrate.  
     
     
         25 . The method according to  claim 22 , wherein, in the third step, the insulating film is formed by sequentially forming a first silicon oxide film, a second silicon oxide film and a silicon nitride film on the semiconductor substrate.  
     
     
         26 . The method according to  claim 22 , wherein, in the third step, the insulating film is formed by sequentially forming a first silicon oxide film, a silicon nitride film and a second silicon oxide film on the semiconductor substrate.  
     
     
         27 . The method according to  claim 22 , wherein, in the second step, the lower electrode is formed into a plurality of concavities, a plurality of convexities, or a plurality of stripe-shaped convexities.  
     
     
         28 . A method for manufacturing a non-volatile semiconductor memory device, comprising: 
 a first step of forming an element isolation insulating film in a semiconductor substrate in order to define a storage circuit region, a logic circuit region and a capacitor region;    a second step of forming a concavity in the semiconductor substrate included in the capacitor region, and introducing impurities into the semiconductor substrate from a wall surface and a bottom surface of the concavity to form a lower electrode;    a third step of sequentially forming a first insulating film, a second insulating film and a first conductive film on the semiconductor substrate including the lower electrode;    a fourth step of forming in the storage circuit region a charge storage film from the first insulating film and the second insulating film and a first gate electrode from the first conductive film;    a fifth step of forming in the logic circuit region a gate insulating film from the first insulating film and the second insulating film and a second gate electrode from the first conductive film; and    a sixth step of forming in the capacitor region a capacitor capacitance insulating film from the first insulating film and the second insulating film and an upper electrode from the first conductive film.    
     
     
         29 . The method according to  claim 28 , wherein, in the third step, the second insulating film is formed by nitriding an upper portion of the first insulating film.  
     
     
         30 . The method according to  claim 28 , wherein, in the third step, the second insulating film is formed by depositing a silicon nitride film on the first insulating film.  
     
     
         31 . The method according to  claim 28 , wherein the first insulating film is a silicon oxide film.  
     
     
         32 . The method according to  claim 28 , wherein, in the second step, the lower electrode is formed into a plurality of concavities, a plurality of convexities, or a plurality of stripe-shaped convexities.  
     
     
         33 . A method for manufacturing a non-volatile semiconductor memory device, comprising: 
 a first step of forming an element isolation insulating film in a semiconductor substrate in order to define a storage circuit region, a logic circuit region and a capacitor region;    a second step of forming a concavity in the semiconductor substrate included in the capacitor region, and introducing impurities into the semiconductor substrate from a wall surface and a bottom surface of the concavity to form a lower electrode;    a third step of forming a first insulating film on the semiconductor substrate including the lower electrode;    a fourth step of removing the first insulating film included in the logic circuit region;    a fifth step of sequentially depositing a second insulating film, a third insulating film and a first conductive film on an exposed surface of the semiconductor substrate in the logic circuit region and on the first insulating film in the storage circuit region and the capacitor region;    a sixth step of forming in the storage circuit region a charge storage film from the first insulating film, the second insulating film and the third insulating film and a first gate electrode from the first conductive film;    a seventh step of forming in the logic circuit region a gate insulating film from the second insulating film and the third insulating film and a second gate electrode from the first conductive film; and    an eighth step of forming in the capacitor region a capacitor capacitance insulating film from the first insulating film, the second insulating film and the third insulating film and an upper electrode from the first conductive film.    
     
     
         34 . The method according to  claim 33 , wherein each of the first insulating film and the second insulating film is a silicon oxide film.  
     
     
         35 . The method according to  claim 22 , wherein the third insulating film is a silicon nitride film.  
     
     
         36 . The method according to  claim 33 , wherein, in the second step, the lower electrode is formed into a plurality of concavities, a plurality of convexities, or a plurality of stripe-shaped convexities.  
     
     
         37 . A method for manufacturing a non-volatile semiconductor memory device, comprising: 
 a first step of forming an element isolation insulating film in a semiconductor substrate in order to define a storage circuit region, a logic circuit region and a capacitor region;    a second step of forming a concavity in the semiconductor substrate included in the capacitor region, and introducing impurities into the semiconductor substrate from a wall surface and a bottom surface of the concavity to form a lower electrode;    a third step of sequentially forming a first insulating film and a second insulating film on the semiconductor substrate including the lower electrode;    a fourth step of sequentially removing the second insulating film and the first insulating film which are included in the logic circuit region;    a fifth step of sequentially depositing a third insulating and a first conductive film on an exposed surface of the semiconductor substrate in the logic circuit region and on the second insulating film in the storage circuit region and the capacitor region;    a sixth step of forming in the storage circuit region a charge storage film from the first insulating film, the second insulating film and the third insulating film and a first gate electrode from the first conductive film;    a seventh step of forming in the logic circuit region a gate insulating film from the third insulating film and a second gate electrode from the first conductive film; and    an eighth step of forming in the capacitor region a capacitor capacitance insulating film from the first insulating film, the second insulating film and the third insulating film and an upper electrode from the first conductive film.    
     
     
         38 . The method according to  claim 37 , wherein each of the first insulating film and the third insulating film is a silicon oxide film.  
     
     
         39 . The method according to  claim 37 , wherein the second insulating film is a silicon nitride film.  
     
     
         40 . The method according to  claim 37 , wherein, in the second step, the lower electrode is formed into a plurality of concavities, a plurality of convexities, or a plurality of stripe-shaped convexities.  
     
     
         41 . A method for manufacturing a non-volatile semiconductor memory device, comprising: 
 a first step of forming an element isolation insulating film in a semiconductor substrate in order to define a storage circuit region and a capacitor region;    a second step of depositing a first conductive film on the semiconductor substrate and etching the first conductive film in the capacitor region to form a lower electrode having an increased surface area;    a third step of sequentially forming an insulating film and a second conductive film on the semiconductor substrate including the lower electrode;    a fourth step of forming in the storage circuit region a charge storage film from the insulating film and a first gate electrode from the second conductive film; and    a fifth step of forming in the capacitor region a capacitor capacitance insulating film from the insulating film and an upper electrode from the second conductive film.    
     
     
         42 . The method according to  claim 41 , wherein, in the third step, the insulating film is formed by depositing a silicon oxide film on the semiconductor substrate and then nitriding an upper portion of the deposited silicon oxide film.  
     
     
         43 . The method according to  claim 41 , wherein, in the third step, the insulating film is formed by sequentially depositing a silicon oxide film and a silicon nitride film on the semiconductor substrate.  
     
     
         44 . The method according to  claim 41 , wherein, in the third step, the insulating film is formed by sequentially forming a first silicon oxide film, a second silicon oxide film and a silicon nitride film on the semiconductor substrate.  
     
     
         45 . The method according to  claim 41 , wherein, in the third step, the insulating film is formed by sequentially forming a first silicon oxide film, a silicon nitride film and a second silicon oxide film on the semiconductor substrate.  
     
     
         46 . The method according to  claim 41 , wherein, in the second step, the lower electrode is formed into a plurality of holes, a plurality of island-shaped lower electrode portions, or a plurality of stripe-shaped lower electrode portions.  
     
     
         47 . The method according to  claim 41 , wherein, in the second step, the lower electrode is formed into a plurality of concavities, a plurality of convexities, or a plurality of stripe-shaped convexities.  
     
     
         48 . A method for manufacturing a non-volatile semiconductor memory device, comprising: 
 a first step of forming an element isolation insulating film in a semiconductor substrate in order to define a storage circuit region, a logic circuit region and a capacitor region;    a second step of sequentially forming a first insulating film and a first conductive film on the semiconductor substrate and etching the first conductive film in the capacitor region to form a lower electrode having an increased surface area;    a third step of sequentially removing the first conductive film and the first insulating film in the storage circuit region and the logic circuit region;    a fourth step of sequentially forming a second insulating film, a third insulating film and a second conductive film on the semiconductor substrate including the lower electrode;    a fifth step of forming in the storage circuit region a charge storage film from the second insulating film and the third insulating film and a first gate electrode from the second conductive film;    a sixth step of forming in the logic circuit region a gate insulating film from the second insulating film and the third insulating film and a second gate electrode from the second conductive film; and    a seventh step of forming in the capacitor region a capacitor capacitance insulating film from the second insulating film and the third insulating film and an upper electrode from the second conductive film.    
     
     
         49 . The method according to  claim 48 , wherein, in the fourth step, the third insulating film is formed by nitriding an upper portion of the second insulating film.  
     
     
         50 . The method according to  claim 48 , wherein, in the fourth step, the third insulating film is formed by depositing a silicon nitride film on the second insulating film.  
     
     
         51 . The method according to  claim 48 , wherein the second insulating film is a silicon oxide film.  
     
     
         52 . The method according to  claim 48 , wherein, in the second step, the lower electrode is formed into a plurality of holes, a plurality of island-shaped lower electrode portions, or a plurality of stripe-shaped lower electrode portions.  
     
     
         53 . The method according to  claim 48 , wherein, in the second step, the lower electrode is formed into a plurality of concavities, a plurality of convexities, or a plurality of stripe-shaped convexities.  
     
     
         54 . A method for manufacturing a non-volatile semiconductor memory device, comprising: 
 a first step of forming an element isolation insulating film in a semiconductor substrate in order to define a storage circuit region, a logic circuit region and a capacitor region;    a second step of sequentially forming a first insulating film and a first conductive film on the semiconductor substrate and etching the first conductive film in the capacitor region to form a lower electrode having an increased surface area;    a third step of sequentially removing the first conductive film and the first insulating film in the storage circuit region and the logic circuit region;    a fourth step of forming a second insulating film on the semiconductor substrate including the lower electrode;    a fifth step of removing the second insulating film included in the logic circuit region;    a sixth step of sequentially depositing a third insulating film, a fourth insulating film and a second conductive film on an exposed surface of the semiconductor substrate in the logic circuit region and on the second insulating film in the storage circuit region and the capacitor region;    a seventh step of forming in the storage circuit region a charge storage film from the second insulating film, the third insulating film and the fourth insulating film and a first gate electrode from the second conductive film;    an eighth step of forming in the logic circuit region a gate insulating film from the third insulating film and the fourth insulating film and a second gate electrode from the second conductive film; and    a ninth step of forming in the capacitor region a capacitor capacitance insulating film from the second insulating film, the third insulating film and the fourth insulating film and an upper electrode from the second conductive film.    
     
     
         55 . The method according to  claim 54 , wherein each of the second insulating film and the third insulating film is a silicon oxide film.  
     
     
         56 . The method according to  claim 54 , wherein the fourth insulating film is a silicon nitride film.  
     
     
         57 . The method according to  claim 54 , wherein, in the second step, the lower electrode is formed into a plurality of holes, a plurality of island-shaped lower electrode portions, or a plurality of stripe-shaped lower electrode portions.  
     
     
         58 . The method according to  claim 54 , wherein, in the second step, the lower electrode is formed into a plurality of concavities, a plurality of convexities, or a plurality of stripe-shaped convexities.  
     
     
         59 . A method for manufacturing a non-volatile semiconductor memory device, comprising: 
 a first step of forming an element isolation insulating film in a semiconductor substrate in order to define a storage circuit region, a logic circuit region and a capacitor region;    a second step of sequentially forming a first insulating film and a first conductive film on the semiconductor substrate and etching the first conductive film in the capacitor region to form a lower electrode having an increased surface area;    a third step of sequentially removing the first conductive film and the first insulating film which are included in the storage circuit region and the logic circuit region;    a fourth step of sequentially forming a second insulating film and a third insulating film on the semiconductor substrate including the lower electrode;    a fifth step of sequentially removing the third insulating film and the second insulating film which are included in the logic circuit region;    a sixth step of sequentially depositing a fourth insulating film and a second conductive film on an exposed surface of the semiconductor substrate in the logic circuit region and on the third insulating film in the storage circuit region and the capacitor region;    a seventh step of forming in the storage circuit region a charge storage film from the second insulating film, the third insulating film and the fourth insulating film and a first gate electrode from the second conductive film;    an eighth step of forming in the logic circuit region a gate insulating film from the fourth insulating film and a second gate electrode from the second conductive film; and    a ninth step of forming in the capacitor region a capacitor capacitance insulating film from the second insulating film, the third insulating film and the fourth insulating film and an upper electrode from the second conductive film.    
     
     
         60 . The method according to  claim 59 , wherein each of the second insulating film and the fourth insulating film is a silicon oxide film.  
     
     
         61 . The method according to  claim 59 , wherein the third insulating film is a silicon nitride film.  
     
     
         62 . The method according to  claim 59 , wherein, in the second step, the lower electrode is formed into a plurality of holes, a plurality of island-shaped lower electrode portions, or a plurality of stripe-shaped lower electrode portions.  
     
     
         63 . The method according to  claim 59 , wherein, in the second step, the lower electrode is formed into a plurality of concavities, a plurality of convexities, or a plurality of stripe-shaped convexities.