Tamdem crossbar switch with ultra low crosstalk

Abstract

Switching apparatus and method in an array having plural inputs and plural outputs crossing each other at a plurality of crosspoints. First and second tandem switches are disposed at each crosspoint, between a respective input and a respective output. A shunt capacitor is coupled to each first and second switch and to ground, to short crosstalk in the inputs and outputs. A method of making a semiconductor switch array is also provided.

What is claimed is:  
     
         1 . Telecommunications switching apparatus for an array having a plurality of inputs and a plurality of outputs, comprising: 
 a plurality of switching elements, each coupled to a respective input and to a respective output; and    shunt capacitance structure coupled to the switching elements to suppress crosstalk between the inputs and the outputs.    
     
     
         2 . Apparatus according to  claim 1 , wherein said shunt capacitance structure comprises a plurality of shunt capacitance elements, each coupled to a respective one of the switching elements and to ground.  
     
     
         3 . Apparatus according to  claim 2 , wherein a shunt capacitance of each shunt capacitance element is greater than a parasitic capacitance of the respective switching element.  
     
     
         4 . Apparatus according to  claim 2 , wherein each switching element has an ON resistance which is less than an impedance of the respective shunt capacitance element.  
     
     
         5 . Apparatus according to  claim 1 , further comprising another plurality of switching elements respectively coupled in tandem with said plurality of switching elements.  
     
     
         6 . Apparatus according to  claim 5 , wherein each of said another plurality of switching elements is coupled in series with a respective one of said plurality of switching elements, between said respective input and said respective output.  
     
     
         7 . Apparatus according to  claim 6 , wherein said shunt capacitance structure comprises a shunt capacitor coupled to each of the switching elements and to ground.  
     
     
         8 . Apparatus according to  claim 1 , wherein said switching apparatus is disposed on multiple horizontal levels, with the plurality of switching elements being disposed at switch crosspoints.  
     
     
         9 . Apparatus according to  claim 8 , wherein said plurality of switching elements comprises a plurality of series thyristors and a plurality of shunt thyristors, and wherein said shunt capacitance structure comprises a plurality of thin film capacitors disposed on a substrate.  
     
     
         10 . Apparatus according to  claim 1 , wherein said plurality of switching elements comprises 1000 switching elements.  
     
     
         11 . Apparatus according to  claim 1 , further comprising structure which row-column addresses said plurality of switching elements.  
     
     
         12 . Apparatus according to  claim 1 , wherein said switching apparatus comprises a microwave switching apparatus.  
     
     
         13 . Apparatus according to  claim 1 , wherein said switching apparatus is disposed on a stripline integrated circuit.  
     
     
         14 . Microwave switching apparatus in an array having plural inputs and plural outputs crossing each other at a plurality of crosspoints, comprising: 
 a plurality of first switches, each disposed at a corresponding crosspoint between a respective input and a respective output; and    a plurality of second switches, each disposed in series with a respective first switch.    
     
     
         15 . Apparatus according to  claim 14 , wherein each first switch comprises a series thyristor, and wherein each second switch comprises a shunt thyristor.  
     
     
         16 . Apparatus according to  claim 15 , further comprising a plurality of shunt capacitors, each coupled to a respective shunt thyristor.  
     
     
         17 . Apparatus according to  claim 16 , wherein said switching apparatus is disposed in a monolithic integrated circuit.  
     
     
         18 . Apparatus according to  claim 16 , wherein a shunt capacitance of each shunt capacitor is larger than a parasitic capacitance of each of the respective first and second switches when OFF.  
     
     
         19 . Apparatus according to  claim 16 , wherein an impedance of each shunt capacitor is larger than a series resistance of each of the respective first and second switches when ON.  
     
     
         20 . Apparatus according to  claim 16 , wherein said switching apparatus has a signal-to-noise ratio greater than 30 dB.  
     
     
         21 . A microwave switch array, comprising: 
 a substrate;    a plurality of signal inputs disposed on said substrate;    a plurality of signal outputs disposed on said substrate and crossing said plurality of signal inputs at a plurality of crosspoints;    a plurality of tandem semiconductor switches respectively disposed at the crosspoints, each tandem switch comprising first and second series-connected switches; and    a plurality of semiconductor shunt capacitance elements respectively disposed at the crosspoints and coupled to respective first and second switches and to ground, to ground noise signals.    
     
     
         22 . A switch array according to  claim 21 , wherein each said first and second switch comprises a thyristor.  
     
     
         23 . A switch array according to  claim 21 , wherein, where a shunt capacitance of each shunt capacitance element is C s , and wherein a parasitic capacitance of a respective OFF thyristor is C OFF , C s >>C OFF .  
     
     
         24 . A switch array according to  claim 21 , wherein, where a parallel shunt capacitance is Z C , and wherein a series resistance of a respective ON thyristor is R ON , Z C >R ON .  
     
     
         25 . A switch array according to  claim 21 , wherein said substrate has no amplification circuitry disposed thereon.  
     
     
         26 . A switch array according to  claim 21 , wherein said plurality of signal inputs and said plurality of signal outputs comprise stripline transmission lines.  
     
     
         27 . A switch array according to  claim 21 , wherein said plurality of signal inputs and said plurality of signal outputs comprise microstrip transmission lines.  
     
     
         28 . A telecommunications switching method in an array having (i) a plurality of inputs and a plurality of outputs, (ii) a plurality of switching elements, each coupled to a respective input and to a respective output, and (iii) shunt capacitance structure coupled to the switching elements, comprising the steps of: 
 switching ON a switching element to pass a signal from a respective input to a respective output;    grounding shunt capacitance structure in switching elements adjacent to the ON switching element to suppress crosstalk between inputs and the outputs adjacent said respective input and said respective output.    
     
     
         29 . A method according to  claim 28 , wherein said shunt capacitance structure comprises a plurality of shunt capacitance elements, each coupled to a respective one of the switching elements and to ground.  
     
     
         30 . A method according to  claim 29 , wherein a shunt capacitance of each shunt capacitance element is greater than a parasitic capacitance of the respective switching element.  
     
     
         31 . A method according to  claim 29 , wherein each switching element has an ON resistance which is less than an impedance of the respective shunt capacitance element.  
     
     
         32 . A method according to  claim 28 , wherein another plurality of switching elements are respectively coupled in tandem with said plurality of switching elements, and wherein said switching ON step includes the step of switching ON one of said plurality of another switching elements with the ON switching element.  
     
     
         33 . A method according to  claim 32 , wherein each of said another plurality of switching elements is coupled in series with a respective one of said plurality of switching elements, between said respective input and said respective output.  
     
     
         34 . A method according to  claim 33 , wherein said shunt capacitance structure comprises a shunt capacitor coupled to each of the switching elements and to ground.  
     
     
         35 . A method according to  claim 28 , wherein said switching apparatus is disposed on multiple horizontal levels, with the plurality of switching elements being disposed at switch crosspoints.  
     
     
         36 . A method according to  claim 35 , wherein said plurality of switching elements comprises a plurality of series thyristors and a plurality of shunt thyristors, and wherein said shunt capacitance structure comprises a plurality of thin film capacitors disposed on a substrate.  
     
     
         37 . A method according to  claim 28 , further comprising the step of row-column addressing said plurality of switching elements to cause said switching ON step.  
     
     
         38 . A microwave switching method in an array having plural inputs and plural outputs crossing each other at a plurality of crosspoints, comprising the steps of: 
 providing a plurality of first switches, each disposed at a corresponding crosspoint between a respective input and a respective output;    providing a plurality of second switches, each disposed in series with a respective first switch;    switching ON at least one of said plurality of first switches and at least one of plurality of second switches to cause a signal to flow from an input to an output; and    grounding noise in inputs and outputs which are unconnected to the ON switches.    
     
     
         39 . A method according to  claim 38 , wherein each first switch comprises a series thyristor, and wherein each second switch comprises a shunt thyristor.  
     
     
         40 . A method according to  claim 39 , further comprising the step of providing a plurality of shunt capacitors, each coupled to a respective shunt thyristor, to perform said grounding step.  
     
     
         41 . A method according to  claim 40 , wherein said steps are performed on a monolithic integrated circuit.  
     
     
         42 . A method according to  claim 40 , wherein a shunt capacitance of each shunt capacitor is larger than a parasitic capacitance of each of the respective first and second switches when OFF.  
     
     
         43 . A method according to  claim 40 , wherein an impedance of each shunt capacitor is larger than a series resistance of each of the respective first and second switches when ON.  
     
     
         44 . A method according to  claim 40 , wherein said switching method provides output signals having a signal-to-noise ratio greater than 30 dB.  
     
     
         45 . A microwave switching method in an array having (i) a substrate, (ii) a plurality of signal inputs disposed on said substrate, (iii) a plurality of signal output disposed on said substrate and crossing said plurality of signal inputs at a plurality of crosspoints, (iv) a plurality of tandem semiconductor switches respectively disposed at the crosspoints, each tandem switch comprising first and second series-connected switches, and (v) a plurality of semiconductor shunt capacitance elements respectively disposed at the crosspoints and coupled to respective first and second switches and to ground, comprising the steps of: 
 switching ON respective first and second series-connected switches disposed at a crosspoint to pass a signal from a respective input to a respective output; and    grounding noise signals in OFF first and second series-connected switches through their respective shunt capacitance elements.    
     
     
         46 . A method according to  claim 45 , wherein each said first and second switch comprises a thyristor.  
     
     
         47 . A method according to  claim 45 , wherein, where a shunt capacitance of each shunt capacitance element is C s , and wherein a parasitic capacitance of a respective OFF thyristor is C OFF , C s >>C OFF .  
     
     
         48 . A method according to  claim 45 , wherein, where a parallel shunt capacitance is Z C , and wherein a series resistance of a respective ON thyristor is R ON , Z C >>R ON .  
     
     
         49 . A method according to  claim 45 , wherein no amplification step is performed on said substrate.  
     
     
         50 . A method of making a microwave switch array, comprising the steps of: 
 providing a substrate;    forming a plurality of signal inputs on said substrate;    forming a plurality of signal output on said substrate and crossing said plurality of signal inputs at a plurality of crosspoints;    forming a plurality of tandem semiconductor switches respectively disposed at the crosspoints, each tandem switch comprising first and second series-connected switches; and    forming a plurality of semiconductor shunt capacitance elements respectively at the crosspoints and coupled to respective first and second switches and to ground.    
     
     
         51 . A method according to  claim 50 , wherein each said first and second switch comprises a thyristor.  
     
     
         52 . A method according to  claim 50 , wherein, where a shunt capacitance of each shunt capacitance element is C s , and wherein a parasitic capacitance of a respective OFF thyristor is C OFF , C s >>C OFF .  
     
     
         53 . A method according to  claim 50 , wherein, where a parallel shunt capacitance is Z C , and wherein a series resistance of a respective ON thyristor is R ON , Z C >>R ON .  
     
     
         54 . A method according to  claim 50 , wherein said substrate has no amplification circuitry disposed thereon.  
     
     
         55 . A method according to  claim 50 , wherein said plurality of signal inputs and said plurality of signal outputs comprise stripline transmission lines.  
     
     
         56 . A method according to  claim 50 , wherein said plurality of signal inputs and said plurality of signal outputs comprise microstrip transmission lines.  
     
     
         57 . A telecommunications switching array comprising: 
 a plurality of inputs;    a plurality of outputs;    a plurality of switching elements, each coupled to a respective input and to a respective output; and    shunt capacitance structure coupled to the switching elements to suppress crosstalk between the inputs and the outputs.    
     
     
         58 . An array according to  claim 57 , wherein said shunt capacitance structure comprises a three plate thin film capacitor having top and bottom plates grounded.  
     
     
         59 . An array according to  claim 58 , further comprising a substrate disposed between said inputs and said outputs, and wherein said three plate thin film capacitor is disposed over an upper surface of said substrate.  
     
     
         60 . An array according to  claim 57 , wherein said inputs and said outputs comprise stripline traces.  
     
     
         61 . An array according to  claim 57 , wherein said inputs and said outputs comprise microstrip traces.  
     
     
         62 . An array according to  claim 57 , wherein said a plurality of inputs, said plurality of outputs, said plurality of switching elements, and said shunt capacitance are formed in an integrated circuit, and further comprising: 
 an upper ground plane;    another ground plane, disposed under said upper ground plane;    a glass substrate, disposed under said another ground plane;    a further ground plane, disposed under said glass substrate;    a lower ground plane, disposed under said further ground plane;    a plurality of row traces disposed between said upper and said another ground plane; and    a plurality of column traces disposed between said lower ground plane and said further ground plane.    
     
     
         63 . An array according to  claim 57 , wherein said a plurality of inputs, said plurality of outputs, said plurality of switching elements, and said shunt capacitance are formed in an integrated circuit, and further comprising: 
 an upper ground plane;    another ground plane, disposed under said upper ground plane;    a glass substrate, disposed under said another ground plane;    a further ground plane, disposed under said glass substrate;    a lower ground plane, disposed under said further ground plane;    a plurality of column traces disposed between said upper and said another ground plane; and    a plurality of row traces disposed between said lower ground plane and said further ground plane.