Transcribing original substrate for a wiring pattern

Abstract

A wiring pattern formation method for forming a wiring pattern on a wafer by using a transcribing operation includes a transcribing step of thermally pressing and adhering a transcribing original substrate 19 that contains a metallic wiring layer 15 to be transcribed and has a linear expansion coefficient in which a dimensional error from a wafer 10 is within a predetermined range in a heated condition, on the wafer 10, and then adhering and transcribing the metallic wiring layer 15.

What is claimed is:  
     
         1 . A wiring pattern formation method for forming a wiring pattern on a substrate by using a transcribing operation; 
 further including a transcribing step of thermally pressing and adhering a transcribing original substrate that contains a wiring layer to be transcribed and has a linear expansion coefficient in which a dimensional error from the substrate is within a predetermined range in a heated condition, on the substrate, and then adhering and transcribing the wiring layer.    
     
     
         2 . A wiring pattern formation method according to  claim 1 , wherein the transcribing original substrate comprising the wiring layer formed on a base substrate, and an insulation layer compose of an adhesive formed on the wiring layer for transcribing the wiring layer onto the substrate.  
     
     
         3 . A wiring pattern formation method according to  claim 1 , wherein the wiring layer is transcribing onto the substrate through the a insulation layer compose of an adhesive formed on the substrate.  
     
     
         4 . A wiring pattern formation method according to  claim 1 , further including a removing step of removing the transcribing original substrate after the wiring layer is left on the substrate, after the transcribing step.  
     
     
         5 . A wiring pattern formation method according to  claim 4 , wherein the removal of the transcribing original substrate after the wiring layer is left is carried out by using any of a mechanically removing method, an etching method and a grinding method.  
     
     
         6 . A wiring pattern formation method according to  claim 4 , wherein the transcribing step and the removing step are repeatedly carried out by using a plurality of the transcribing original substrates, and a multiple-layer wiring is formed on the substrate.  
     
     
         7 . A wiring pattern formation method according to  claim 1 , wherein the substrate is a wafer in which a circuit is already formed.  
     
     
         8 . A wiring pattern formation method according to  claim 1 , wherein a linear expansion coefficient of the transcribing original substrate is within a range of ±2 ppm/degree with respect to the substrate.  
     
     
         9 . A transcribing original substrate used for a wiring pattern formation method for forming a wiring pattern on a substrate by using a transcribing operation, 
 wherein the transcribing original substrate having a wiring layer to be transcribed, and has a linear expansion coefficient in which a dimensional error from the substrate is within a predetermined range in a heated condition resulting from a thermally pressing and adhering operation for the transcribing operation.    
     
     
         10 . A transcribing original substrate used for a wiring pattern formation method according to  claim 9 , wherein the transcribing original substrate comprising; abase substrate; and the wiring layer on the base substrate.  
     
     
         11 . A transcribing original substrate used for a wiring pattern formation method according to  claim 10 , wherein the base substrate is removed after transcribed the wiring layer is left on the substrate.  
     
     
         12 . A transcribing original substrate used for a wiring pattern formation method according to  claim 9 , wherein the transcribing original substrate having an insulation layer for adhering the wiring layer on the substrate.  
     
     
         13 . A transcribing original substrate used for a wiring pattern formation method according to  claim 12 , wherein the insulation layer is composed of adhesive and formed on the wiring layer.  
     
     
         14 . A transcribing original substrate used for a wiring pattern formation method according to  claim 9 , wherein the linear expansion coefficient of the transcribing original substrate is within a range of ±2 ppm/degree with respect to the substrate.  
     
     
         15 . A transcribing original substrate used for a wiring pattern formation method according to  claim 9 , wherein the transcribing original substrate has a plane shape similar to that of the substrate.  
     
     
         16 . A method for manufacturing a semiconductor device, the method comprising the steps of: 
 thermally pressing and adhering a transcribing original substrate that having a wiring layer to be transcribed and has a linear expansion coefficient in which a dimensional error from a substrate is within a predetermined range in a heated condition onto the substrate,and adhering and transcribing the wiring layer; 
 wherein the substrate is a wafer in which a circuit is already formed,  
   sequentially repeating the transcribing operation for forming a multiple wiring layer on the wafer;    coating a part except an outer electrode formation portion in the wiring layer with an insulator, and mounting an outer electrode terminal at the outer electrode formation portion; and    cutting the wafer into respective pieces, and generating a semiconductor device.    
     
     
         17 . A semiconductor device comprising: 
 a multiple wiring layer formed on a wafer, wherein the multiple wiring layer is formed by thermally pressing and adhering a transcribing original substrate that having a wiring layer to be transcribed and has a linear expansion coefficient in which a dimensional error from a substrate is within a predetermined range in a heated condition onto the substrate and adhering and transcribing the wiring layer, sequentially repeating the transcribing operation;    a substrate composed of respective pieces each having the multiple wiring layer since the wafer is cut; and    an outer electrode terminal mounted at an outer electrode formation portion of the multiple wiring layer.