Semiconductor storage device having memory chips in a stacked structure

Abstract

Two memory chips each being subjected to memory accesses in 2-bit units are assembled into a stacked structure by placing their back surfaces one over the other, so as to make memory accesses in 4-bit units. A memory module is so constructed that a plurality of such semiconductor storage devices, in each of which two memory chips each being subjected to memory accesses in 2-bit units are assembled into a stacked structure by placing their back surfaces one over the other, so as to make memory accesses in 4-bit units, are mounted on a mounting circuit board which is square and which is formed with electrodes along one latus thereof.

We claim:  
     
         1 . A semiconductor storage device comprising two memory chips each being subjected to memory accesses in 2-bit units, sealed in a state where their back surfaces are opposite to each other, so as to make memory accesses in 4-bit units.  
     
     
         2 . A semiconductor storage device according to  claim 1 , wherein said two memory chips are placed one over the other so as to hold their back surfaces in touch with each other, and that, at least front surfaces of said two memory chips are in touch with a sealing resin.  
     
     
         3 . A semiconductor storage device according to  claim 2 , wherein each of said memory chips is divided into a plurality of memory banks, and that, when said memory chips have been placed one over the other so as to hold their back surfaces in touch, positions of the memory banks to which the same address is assigned are made different on said back surfaces of said memory chips.  
     
     
         4 . A semiconductor storage device according to any of claims  1  through  3 , wherein a thickness of said semiconductor storage device in which said two memory chips are stacked and sealed is equal to or less than a thickness of a semiconductor storage device whose storage capacity is half of or equal to a storage capacity of the former semiconductor storage device, and in which a single memory chip is sealed.  
     
     
         5 . A semiconductor storage device according to any of claims  1  through  4 , wherein the stacked memory chips have a facility by which a plurality of sorts of data inputting/outputting in plural-bit units, including the memory accesses in 2-bit units, are realized by employing wiring means or bonding wire and by setting signal transmission paths or signal levels of said stacked memory chips.  
     
     
         6 . A semiconductor storage device according to  claim 5 , wherein the plural-bit units are of four sorts; 2-bit units, 4-bit units, 8-bit units and 16-bit units.  
     
     
         7 . A semiconductor storage device according to  claim 2  or  3 , 
 wherein said semiconductor storage device is formed with leads so as to extend from both side surfaces of a square resin-sealing package in a longitudinal direction thereof,  
 wherein the 4 bits correspond to leads for data consisting of a first lead through a fourth lead,  
 wherein a pair of the first and second leads, and a pair of the third and fourth leads are separately disposed at positions symmetric with respect to a center line parallel to the longitudinal direction, on both sides of said square resin-sealing package and  
 wherein that electrodes corresponding respectively to data terminals of 2 bits are electrically connected to said first lead and second lead in one of said two memory chips, while electrodes corresponding respectively to data terminals of 2 bits are electrically connected to said third lead and fourth lead in the other memory chip.  
 
     
     
         8 . A semiconductor storage device comprising: 
 two memory chips each being subjected to memory accesses in 2-bit units, assembled into a stacked structure so as to make memory accesses in 4-bit units,    wherein each of said two memory chips being provided with leads of tape state on a front surface thereof, and, at least, the front surface part lying in touch with a sealing resin except a back surface of said each memory chip.    
     
     
         9 . A semiconductor storage device according to  claim 8 , wherein the thickness of said semiconductor storage device made into said stacked structure is equal to or less than the thickness of a semiconductor storage device whose storage capacity is half of or equal to the storage capacity of the former semiconductor storage device, and in which a single memory chip is included.  
     
     
         10 . A semiconductor storage device according to  claim 8 , wherein said each memory chip has a facility by which a plurality of sorts of data inputting/outputting in plural-bit units, including the memory accesses in 2-bit units, are realized by employing wiring means or bonding wire and by setting signal transmission paths or signal levels of said each memory chip.  
     
     
         11 . A semiconductor storage device according to  claim 10 , wherein the plural-bit units are of four sorts; 2-bit units, 4-bit units, 8-bit units and 16-bit units.  
     
     
         12 . A semiconductor storage device comprising: 
 two memory chips sealed by a sealing member in a state where their back surfaces are placed one over the other,    wherein each of said two memory chips are divided into a plurality of memory areas,    wherein said each memory chip is subjected to memory accesses to activated ones of said memory areas in 2-bit units, thereby to subject said two memory chips to memory accesses in 4-bit units, and    wherein positions of the activated memory areas are different on the surfaces of said two memory chips placed on each other.    
     
     
         13 . A semiconductor storage device comprising: 
 first and second memory chips;    a sealing member which seals said first and second memory chips in a state where their back surfaces are placed one over the other;    first and second leads which extend from a first latus of said sealing member to the inside and outside said sealing member; and    third and fourth leads which extend from a second latus of said sealing member opposite to said first latus, to the inside and outside said sealing member,    wherein each of said first and second memory chips includes first, second, third and fourth terminals for outputting data, which are arranged along a straight line being parallel to longer latera of said each memory chip and passing through the central parts of shorter latera thereof, on a circuit forming surface of said each memory chip,    wherein the second terminal is arranged at a position nearer to the first terminal between said first terminal and third terminal,    wherein said third terminal is arranged at a position nearer to the fourth terminal between said second terminal and fourth terminal,    wherein the first lead and the fourth lead are arranged at positions which oppose with said straight line held therebetween,    wherein the second lead and the third lead are arranged at positions which oppose with said straight line held therebetween and    wherein each of said first and second memory chips outputs data in 2-bit units by employing either of the first and second terminals, and either of the third and fourth terminals, thereby to output data from the first, second, third and fourth leads in 4-bit units.    
     
     
         14 . A semiconductor storage device according to  claim 13 , 
 wherein either of the first and second terminals of the first memory chip and either of the first and second terminals of the second memory chip are selectively connected to said first lead and said fourth lead through pieces of wire, respectively and    wherein either of the third and fourth terminals of said first memory chip and either of the third and fourth terminals of said second memory chip are selectively connected to said second lead and said third lead through pieces of wire, respectively.    
     
     
         15 . A semiconductor storage device according to  claim 14 , wherein each of said first and second memory chips has a construction capable of outputting data in 4-bit units, and that the data of 4 bits are derived from said first, second, third and fourth terminals.  
     
     
         16 . A semiconductor storage device comprising: 
 first and second memory chips;    a sealing member which seals said first and second memory chips in a state where their back surfaces are placed one over the other;    a plurality of leads for addresses, which extend inside and outside said sealing member; and    a plurality of leads for data, which extend inside and outside said sealing member,    wherein each of said leads for addresses is bifurcated within said sealing member, bifurcated leads being respectively extended over front surfaces of said first and second memory chips,    wherein each of said leads for data is extended over the front surface of at least one of said first and second memory chips,    wherein each of said first and second memory chips includes a plurality of address terminals and a plurality of data terminals on its front surface,    wherein the corresponding address terminals of said first and second memory chips are connected in common with the bifurcated leads for addresses through pieces of wire, respectively,    wherein said data terminals on the first memory chip and said data terminals on the second memory chip are isolated and connected to the corresponding leads for data through pieces of wire and    wherein data are outputted in 2-bit units from each of said first and second memory chips, thereby to output data from said leads for data in 4-bit units.    
     
     
         17 . A semiconductor storage device according to  claim 16 , wherein said leads for data are asymmetric as to their lengths extending toward said first and second memory chips.  
     
     
         18 . A semiconductor storage device comprising a memory chip for which four sorts of data outputting in 2-bit units, 4-bit units, 8-bit units and 16-bit units can be selected by employing wiring or bonding wire and by setting signal transmission paths or signal levels of said memory chip.  
     
     
         19 . A memory module comprising a plurality of semiconductor storage devices, in each of which two memory chips each being subjected to memory accesses in 2-bit units are sealed in a state where their back surfaces are opposite to each other, so as to make memory accesses in 4-bit units, are disposed on a square mounting circuit board which is formed with electrodes along one latus thereof.  
     
     
         20 . A memory module according to  claim 19 , wherein said two memory chips are placed one over the other so as to hold their back surfaces in touch with each other, and that, at least front surfaces of said two memory chips are in touch with a sealing resin.  
     
     
         21 . A memory module according to  claim 19  or  20 , wherein the thickness of said semiconductor storage device in which said two memory chips are stacked and sealed is equal to or less than the thickness of a semiconductor storage device whose storage capacity is half of or equal to a storage capacity of the former semiconductor storage device, and in which a single memory chip is sealed.  
     
     
         22 . A memory module according to  claim 19  or  20 , wherein said semiconductor storage devices have a facility by which a plurality of sorts of data inputting/outputting in plural-bit units, including the memory accesses in 2-bit units, are realized by setting voltages that are applied to external terminals.  
     
     
         23 . A memory module according to  claim 22 , wherein the plural-bit units are of four sorts; 2-bit units, 4-bit units, 8-bit units and 16-bit units.  
     
     
         24 . A memory module according to any of claims  19  through  23 , wherein a plurality of such memory modules are mounted in a state where their connectors are respectively plugged into a plurality of sockets which are juxtaposed on a circuit board.  
     
     
         25 . A memory module comprising a plurality of semiconductor storage devices, wherein 
 two memory chips, in said semiconductor storage devices, each being subjected to memory accesses in 2-bit units are assembled into a stacked structure so as to make memory accesses in 4-bit units and    wherein each of said two memory chips is provided with tape-like leads on a front surface thereof, and that, at least the front surface part is in touch with a sealing resin except a back surface of said each memory chip.