Programmable resistance memory element and method for making same

Abstract

A programmable resistance memory element. The active volume of memory material is made small by the presence of a small area of contact between the conductive material and the memory material. The area of contact is created by forming a region of conductive material and an intersecting sidewall layer of the memory material. The region of conductive material is preferably a sidewall layer of conductive material.

We claim:  
     
         1 . A programmable memory element, comprising: 
 a region of conductive material embedded in a first region of dielectric material deposited upon a substrate, the conductive material adapted to receive an electrical input signal from a signal source; and    a sidewall layer of programmable resistance memory material embedded in a second dielectric region deposited upon the first region, a bottom surface of the sidewall layer of memory material in electrical communication with a top surface of the region of conductive material.    
     
     
         2 . The memory element of  claim 1 , wherein said sidewall layer of memory material is a sidewall spacer of memory material.  
     
     
         3 . The programmable memory element of  claim 1 , wherein said region of conductive material is a sidewall layer of conductive material.  
     
     
         4 . The programmable memory element of  claim 1 , wherein said region of conductive material is a sidewall spacer of conductive material.  
     
     
         5 . The programmable memory element of  claim 1 , wherein said region of conductive material is a sidewall liner of conductive material.  
     
     
         6 . The programmable memory element of  claim 1 , wherein the region of conductive material and the sidewall layer of memory material have an area of contact having dimensions corresponding to a width of the top surface of said region of conductive material and a width of the bottom surface of said sidewall layer of memory material.  
     
     
         7 . The memory element of  claim 6 , wherein the width of the top surface of the region of conductive material is less than the photolithographic limit.  
     
     
         8 . The memory element of  claim 7 , wherein the width of the top surface of the region of conductive material is less than about 1000 Angstroms.  
     
     
         9 . The memory element of  claim 7 , wherein the width of the top surface of the region of conductive material is less than about 500 Angstroms.  
     
     
         10 . The memory element of  claim 7 , wherein the width of the top surface of the region of conductive material is less than about 300 Angstroms.  
     
     
         11 . The memory element of  claim 7 , wherein the width of the bottom surface of the sidewall layer of memory material is less than the photolithographic limit.  
     
     
         12 . The memory element of  claim 7 , wherein the width of the bottom surface of the sidewall layer of memory material is less than about 1000 Angstroms.  
     
     
         13 . The memory element of  claim 3 , wherein the width of the bottom surface of the sidewall layer of memory material is less than about 500 Angstroms.  
     
     
         14 . The memory element of  claim 3 , wherein the width of the bottom surface of the sidewall layer of memory material is less than about 300 Angstroms.  
     
     
         15 . The memory element of  claim 1 , wherein said top surface and the bottom surface form only one area of contact between the region of conductive material and the sidewall layer of memory material.  
     
     
         16 . The programmable memory element according to  claim 1  wherein the memory material is a phase-change material.  
     
     
         17 . The programmable memory element according to  claim 16  wherein the memory material comprises a chalcogen element.  
     
     
         18 . A programmable memory element, comprising: 
 an electrode; and    a sidewall layer of programmable resistance memory material having a bottom surface in electrical communication with said electrode.    
     
     
         19 . The memory element of  claim 18 , wherein said sidewall layer of programmable resistance material is a sidewall spacer of programmable resistance material.  
     
     
         20 . The memory element of  claim 18 , wherein said electrode includes a sidewall layer of a conductive material, the bottom surface of said sidewall layer of memory material being in electrical communication with a top surface of said sidewall layer of conductive material.  
     
     
         21 . The memory element of  claim 18 , wherein said electrode is a sidewall spacer of conductive material.  
     
     
         22 . The memory element of  claim 18 , wherein said electrode is a liner of conductive material.  
     
     
         23 . The memory element of  claim 20 , wherein the area of contact between said sidewall layer of memory material and said sidewall layer of conductive material is defined by a width of the bottom surface of said sidewall layer of memory material and a width of a top surface of said sidewall layer of conductive material.  
     
     
         24 . The memory element of  claim 23 , wherein the width of the top surface of said electrode has a sublithographic dimension.  
     
     
         25 . The memory element of  claim 23 , wherein the width of the top surface of said electrode has a dimension less than 1000 Angstroms.  
     
     
         26 . The memory element of  claim 23 , wherein the width of the top surface of said electrode has a dimension less than 500 Angstroms.  
     
     
         27 . The memory element of  claim 23 , wherein the width of the bottom surface of said conductive spacer has a sublithographic dimension.  
     
     
         28 . The memory element of  claim 23 , wherein the width of the bottom surface of said conductive spacer has a dimension less than 1000 Angstroms.  
     
     
         29 . The memory element of  claim 23 , wherein the width of the bottom surface of said conductive spacer has a dimension less than 500 Angstroms.  
     
     
         30 . The memory element of  claim 18 , wherein said electrode and said programmable resistance material have only one area of contact.  
     
     
         31 . The memory element of  claim 18 , wherein said programmable resistance material is a phase-change material.  
     
     
         32 . The memory element of  claim 18 , wherein said programmable resistance material includes a chalcogen element.  
     
     
         33 . A method of forming a programmable memory element, comprising the steps of: 
 embedding a region of conductive material in a first region of dielectric material deposited upon a substrate, the conductive material adapted to receive an electrical input signal from a signal source; and    embedding a sidewall layer of memory material in a second dielectric region deposited upon the first region, a bottom surface of the sidewall layer of memory material in electrical communication with a top surface of the region of conductive material; and wherein    the top surface and the bottom surface form only one area of contact between the region of conductive material and the sidewall layer of memory material, the area of contact having dimensions corresponding to a width of the top surface and a width of the bottom surface.    
     
     
         34 . A programmable memory element created by the method according to  claim 33 .  
     
     
         35 . The method according to  claim 33  wherein the step of embedding a region of conductive material in a first region of dielectric material deposited upon a substrate further comprises the steps of: 
 depositing a first dielectric layer upon a substrate, the first dielectric layer having a surface;  
 forming an opening in the surface of the first dielectric layer, the opening having at least one sidewall surface and a top surface;  
 depositing a layer of conductive material upon the surface of the first dielectric layer, the at least one sidewall surface and the top surface;  
 removing portions of the layer of conductive material and the first dielectric layer to form the region of conductive material;  
 depositing a second dielectric layer upon the region of conductive material and any exposed remaining portion of the first dielectric layer; and  
 removing portions of the second dielectric layer to expose the top surface of the region of conductive material.  
 
     
     
         36 . The method according to  claim 35  wherein the step of embedding a sidewall layer of memory material in a second dielectric region deposited upon the first region further comprises the steps of: 
 depositing a third dielectric layer upon the top surface of the region of conductive material and any exposed remaining portions of the first dielectric layer and the second dielectric layer;  
 forming at least one sidewall surface of the third dielectric layer by removing portions of the third dielectric layer to expose a portion of the top surface of the region of conductive material, the at least one sidewall surface of the third dielectric layer lying in a plane, the plane one of perpendicular to the at least one sidewall surface of the opening in the first dielectric layer surface and parallel to a tangent of the at least one sidewall surface of the opening in the first dielectric layer surface;  
 depositing a layer of memory material upon the exposed portion of the top surface of the region of conductive material and any exposed remaining portions of the first dielectric layer and the second dielectric layer and the third dielectric layer; and  
 removing portions of the memory material layer to form the sidewall layer of memory material.  
 
     
     
         37 . The method according to  claim 36 , further comprising the steps of: 
 depositing a fourth dielectric layer upon the sidewall layer of memory material and upon any exposed portions of the first dielectric layer and the second dielectric layer and the third dielectric layer; and    removing portions of the fourth dielectric layer to expose a top surface of the sidewall layer of memory material.    
     
     
         38 . The method according to  claim 37  wherein the step of depositing the fourth dielectric layer further comprises the step of depositing a conformal fourth dielectric layer using one of physical and chemical vapor deposition.  
     
     
         39 . The method according to  claim 37  wherein the step of removing portions of the fourth dielectric layer further comprises the step of performing a chemical mechanical planarization.  
     
     
         40 . The method according to  claim 37 , further comprising the step of: 
 depositing an electrode in contact with the top surface of the sidewall layer of memory material.    
     
     
         41 . The method according to  claim 36  wherein the step of depositing the third dielectric layer further comprises the step of depositing a conformal third dielectric layer using one of physical and chemical vapor deposition.  
     
     
         42 . The method according to  claim 36  wherein the step of removing portions of the fourth dielectric layer further comprises the step of performing a chemical mechanical planarization.  
     
     
         43 . The method according to  claim 36  wherein the step of forming at least one sidewall surface of the third dielectric layer further comprises removing portions of the third dielectric layer using an anisotropic etch.  
     
     
         44 . The method according to  claim 36  wherein the step of depositing a layer of memory material further comprises the step of depositing a conformal layer of memory material.  
     
     
         45 . The method according to  claim 36  wherein the step of depositing a third dielectric layer further comprises the steps of: 
 depositing a nitride layer upon the top surface of the region of conductive material and any exposed remaining portions of the first dielectric layer and the second dielectric layer; and  
 depositing an oxide layer upon the nitride layer.  
 
     
     
         46 . The method according to  claim 35  wherein the step of forming the opening further comprises the step of one of: 
 forming a via to a conductive element upon a surface of the substrate; and  
 forming a trench to the conductive element upon the surface of the substrate.  
 
     
     
         47 . The method according to  claim 35  wherein the step of depositing the layer of conductive material further comprises the step of depositing a conformal layer of conductive material by physical vapor deposition.  
     
     
         48 . The method according to  claim 35  wherein the step of removing portions of the layer of conductive material and the first dielectric layer further comprises the step of: 
 performing at least one of a directional spacer etch and an angular etch.  
 
     
     
         49 . The method according to  claim 35  wherein the step of depositing the second dielectric layer further comprises the step of depositing a conformal layer of dielectric material by one of physical and chemical vapor deposition.  
     
     
         50 . The method according to  claim 35  wherein the step of removing portions of the second dielectric layer further comprises the step of performing a chemical mechanical planarization.  
     
     
         51 . The method according to  claim 35  wherein the step of removing portions of the layer of conductive material and the first dielectric layer comprises the step of performing an anisotropic etch.  
     
     
         52 . The method according to  claim 33 , further comprising the step of: 
 depositing a second electrode upon the sidewall layer of memory material.    
     
     
         53 . The method according to  claim 33 , further comprising the step of: 
 forming an isolation device upon the substrate, the isolation device adapted to receive the electrical input from the signal source, and the isolation device in electrical communication with the region of conductive material.    
     
     
         54 . The method according to  claim 53  wherein the isolation device is a diode.  
     
     
         55 . The method according to  claim 53 , further comprising the step of: 
 depositing an electrode in contact with a top of the sidewall layer of memory material.    
     
     
         56 . The method according to  claim 53 , further comprising the step of: 
 forming a contact between the isolation device and the region of conductive material.    
     
     
         57 . The method according to  claim 33  wherein the width of the top surface of the region of conductive material is less than the photolithographic limit.  
     
     
         58 . The method according to  claim 33  wherein the width of the bottom surface of the sidewall layer of memory material is less than the photolithographic limit.  
     
     
         59 . The method according to  claim 33  wherein the width of the bottom surface of the sidewall layer of memory material is less than the photolithographic limit.  
     
     
         60 . The method according to  claim 33  wherein the width of the top surface of the regon of conductive material is less than about 500 Angstroms.  
     
     
         61 . The method according to  claim 33  wherein the width of the bottom surface of the sidewall layer of memory material is less than about 500 Angstroms.  
     
     
         62 . The method according to  claim 33  wherein the width of the bottom surface of the sidewall layer of memory material is less than about 500 Angstroms.  
     
     
         63 . The method according to  claim 33 , further comprising the step of: 
 forming the region of conductive material in a cup shape wherein the top surface is formed by a circular sidewall layer, the width of which is defined by the difference between an outer circumference and an inner circumference of the circular sidewall layer.    
     
     
         64 . The method according to  claim 33  wherein the memory material is a phase-change material comprising a chalcogen element.  
     
     
         65 . The method according to  claim 33 , further comprising the steps of: 
 forming an isolation device upon the substrate, the isolation device adapted to receive the electrical input from the signal source, and the isolation device in electrical communication with the region of conductive material;    depositing an electrode in contact with a top surface of the sidewall layer of memory material; and    electrically connecting one of a conductive wordline and a conductive bitline to the isolation device and the other of the conductive wordline and the conductive bitline one of being the electrode and electrically connected to the electrode; and wherein 
 the conductive wordline and the conductive bitline are connectable in an array including a plurality of like programmable memory elements and isolation devices.  
   
     
     
         66 . The method according to  claim 33  wherein the top surface is formed by a straight sidewall layer.  
     
     
         67 . The method according to  claim 33  wherein the top surface is formed by a semicircular sidewall layer.