Method for erasing a nonvolatile memory cell formed in a body region of a substrate

Abstract

The present invention provides a novel erase method and apparatus for flash memory cells, with special emphasis on source-side injection cells, which enhances the erase efficiency of the cell. By activating the select-gate terminal of the cell using a negative voltage, it has been found for the first time that the erase performance can be improved. In one preferred embodiment, the present invention provides for three overlapping voltage signals applied to the cell terminals, of which two are negative and one positive. In another preferred embodiment, the memory cell is built on an “internal P-well” within an isolating N-well on the P-type substrate. In this case, by shifting the memory cell's body potential, the erase-mode uses four overlapping erase signals, two of which are negative, and two positive. With experimental data, it is demonstrated that better “magnitude balance” has been achieved for the highest erase voltages of opposite polarities. Since only moderate voltages are needed for the erase operation while maintaining the erase speed, the otherwise stringent requirement on transistor breakdown voltages for on-chip charge pumps and driver circuitry can be relaxed.

What is claimed is:  
     
         1 . A flash EEPROM memory cell comprising: 
 a portion of a semiconductor substrate of P-type conductivity;    a source region and a drain region of N-type conductivity formed in spaced alignment in said substrate with a channel region therebetween;    a first gate insulation layer on a major surface of said substrate;    a floating-gate on said first gate insulation layer, said floating gate extending across a portion of said channel region;    a second gate insulation layer on said floating-gate;    a control-gate on said second gate insulation layer, said control-gate extending across said floating-gate;    a third insulation layer over said control-gate and said channel region; and    a select-gate on said third insulation layer,    wherein said cell is erased by applying a positive voltage to said drain region, a negative voltage to said control-gate, a negative voltage to said select-gate, and allowing the potential of said source region to float, with said substrate connected to ground potential serving as a reference voltage.    
     
     
         2 . The memory cell as in  claim 1  wherein the drain voltage is approximately 5 volts, the control-gate voltage is approximately −10 volts, and the select-gate voltage is approximately −5 volts.  
     
     
         3 . In a flash EEPROM memory cell, said memory cell including a portion of a semiconductor substrate of P-type conductivity; a source region and a drain region of N-type conductivity formed in spaced alignment in said substrate with a channel region therebetween; a first gate insulation layer on a major surface of said substrate; a floating-gate on said first gate insulation layer, said floating-gate extending across a portion of said channel region; a second gate insulation layer on said floating-gate; a control-gate on said second gate insulation layer, said control gate extending across said floating-gate; a third insulation layer over said control-gate and said channel region; and a select-gate on said third insulation layer, the method of erasing said cell comprising the steps of: 
 applying a positive voltage to said drain region;    applying a negative voltage to said control-gate; and    applying a negative voltage to said select-gate,    wherein the potential of said source region floats, and said substrate is connected to ground potential serving as a reference voltage.    
     
     
         4 . A flash EEPROM memory cell comprising: 
 a portion of a semiconductor substrate of P-type conductivity;    a well of N-type conductivity in said substrate;    a well of P-type conductivity in said N-type well, the p-type well forming the cell body;    a source region and a drain region of N-type conductivity formed in spaced alignment in said body with a channel region therebetween;    a first gate insulation layer on a major surface of said body;    a floating-gate on said first gate insulation layer, said floating-gate extending across a portion of said channel region;    a second gate insulation layer on said floating-gate;    a control-gate on said second gate insulation layer, said control gate extending across said floating-gate;    a third insulation layer over said control-gate and said channel region; and    a select-gate on said third insulation layer,    wherein said cell is erased by applying a positive voltage to said drain region, a negative voltage to said control-gate, a negative voltage to said select-gate, a positive voltage to said body region, and allowing the potential of said source region to float, with said substrate connected to ground potential serving as a reference voltage.    
     
     
         5 . The memory cell as in  claim 4  wherein the drain voltage is approximately 7.5 volts, the control-gate voltage is approximately −7.5 volts, and the select-gate voltage is approximately −2.5 volts.  
     
     
         6 . The memory cell as in  claim 5  wherein the body voltage is approximately 2.5 volts.  
     
     
         7 . In a flash EEPROM memory cell, said memory cell including a portion of a semiconductor substrate of P-type conductivity; a well of N-type conductivity in said substrate; a well of P-type conductivity in said N-type well, the p-type well forming the cell body; a source region and a drain region of N-type conductivity formed in spaced alignment in said body with a channel region therebetween; a first gate insulation layer on a major surface of said body; a floating-gate on said first gate insulation layer, said floating gate extending across a portion of said channel region; a second gate insulation layer on said floating-gate; a control-gate on said second gate insulation layer, the control-gate extending over said floating-gate; a third insulation layer over said control-gate and said channel region; and a select-gate formed on said third insulation layer, the method of erasing said cell comprising the steps of: 
 applying a positive voltage to said drain region;    applying a negative voltage to said control-gate;    applying a negative voltage to said select-gate; and    applying a positive voltage to said body region,    wherein the potential of said source region is allowed to float, and said substrate is connected to ground potential serving as a reference voltage.    
     
     
         8 . A flash EEPROM memory cell comprising: 
 a portion of a semiconductor substrate of P-type conductivity;    a well of N-type conductivity in said substrate;    a well of P-type conductivity in said N-type well, the P-type well forming the cell body;    a source region and a drain region of N-type conductivity in spaced alignment in said body with a channel region therebetween;    a first gate insulation layer on a major surface of said body;    a floating-gate on said first gate insulation layer, said floating gate extending across a portion of said channel region;    a second gate insulation on said floating-gate;    a control-gate on said second gate insulation, said control-gate extending across said floating-gate;    a third insulation layer over said control-gate and said channel region; and    a select-gate on said third insulation layer,    wherein said cell is erased by applying a positive voltage to said drain region, a negative voltage to said control-gate, grounding said select-gate, a positive voltage to said body region, and allowing the potential of said source region to float, with said substrate connected to ground potential serving as a reference voltage.    
     
     
         9 . The memory cell as in  claim 8  wherein the drain voltage is approximately 7.5 volts, the control-gate voltage is approximately −8 volts, and the select-gate voltage is approximately 0 volts.  
     
     
         10 . The memory cell as in  claim 9  wherein the body voltage is approximately 2.5 volts.  
     
     
         11 . In a flash EEPROM memory cell, said memory cell including a well of N-type conductivity in said substrate; a well of P-type conductivity in said N-type well, the P-type well forming the cell body; a source region and a drain region of N-type conductivity in spaced alignment in said body with a channel region therebetween; a first gate insulation layer on a major surface of said body; a floating-gate on said first gate insulation layer, said floating gate extending across a portion of said channel region; a second gate insulation on said floating-gate; a control-gate on said second gate insulation, said control-gate extending across said floating-gate; a third insulation layer over said control-gate and said channel region; and a select-gate on said third insulation layer, the method of erasing said cell comprising the steps of: 
 applying a positive voltage to said drain region;    applying a negative voltage to said control-gate;    grounding said select-gate; and    applying a positive voltage to said body region,    wherein the potential of said source region floats, and said substrate is connected to ground potential serving as a reference voltage.    
     
     
         12 . A flash EEPROM memory cell comprising: 
 a portion of a semiconductor substrate of P-type conductivity;    a well of N-type conductivity in said substrate;    a well of P-type conductivity in said N-type well, the p-type well forming the cell body;    a source region and a drain region of N-type conductivity formed in spaced alignment in said body with a channel region therebetween;    a first gate insulation layer on a major surface of said body;    a floating-gate on said first gate insulation layer, said floating-gate extending across said channel region;    a second gate insulation layer on said floating-gate; and    a control-gate on said second gate insulation layer, said control gate extending across said floating-gate,    wherein said cell is erased by applying a positive voltage to said drain region, a negative voltage to said control-gate, a positive voltage to said body region, and allowing the potential of said source region to float, with said substrate connected to ground potential serving as a reference voltage.    
     
     
         13 . In a flash EEPROM memory cell, said memory cell including a portion of a semiconductor substrate of P-type conductivity; a well of N-type conductivity in said substrate; a well of P-type conductivity in said N-type well, the p-type well forming the cell body; a source region and a drain region of N-type conductivity formed in spaced alignment in said body with a channel region therebetween; a first gate insulation layer on a major surface of said body; a floating-gate on said first gate insulation layer, said floating-gate extending across said channel region; a second gate insulation layer on said floating-gate; and a control-gate on said second gate insulation layer, said control gate extending across said floating-gate, the method of erasing said cell comprising the steps of: 
 applying a positive voltage to said drain region;    applying a negative voltage to said control-gate; and    applying a positive voltage to said body region,    wherein the potential of said source region floats, and said substrate is connected to ground potential serving as a reference voltage.    
     
     
         14 . A flash EEPROM memory cell comprising: 
 a portion of a semiconductor substrate of P-type conductivity;    a well of N-type conductivity in said substrate;    a well of P-type conductivity in said N-type well, the p-type well forming the cell body;    a source region and a drain region of N-type conductivity formed in spaced alignment in said body with a channel region therebetween;    a first gate insulation layer on a major surface of said body;    a floating-gate on said first gate insulation layer, said floating-gate extending across said channel region;    a second gate insulation layer on said floating-gate; and a control-gate on said second gate insulation layer, said control gate extending across said floating-gate,    wherein said cell is erased by applying a positive voltage to said source region, a negative voltage to said control-gate electrode, a positive voltage to said body region, and allowing the potential of said drain region to float, with said substrate connected to ground potential serving as a reference voltage.    
     
     
         15 . In a flash EEPROM memory cell, said memory cell including a portion of a semiconductor substrate of P-type conductivity; a well of N-type conductivity in said substrate; a well of P-type conductivity in said N-type well, the p-type well forming the cell body; a source region and a drain region of N-type conductivity formed in spaced alignment in said body with a channel region therebetween; a first gate insulation layer on a major surface of said body; a floating-gate on said first gate insulation layer, said floating-gate extending across said channel region; a second gate insulation layer on said floating-gate; and a control-gate on said second gate insulation layer, said control gate extending across said floating-gate, the method of erasing said cell comprising the steps of: 
 applying a positive voltage to said source region;    applying a negative voltage to said control-gate electrode; and    applying a positive voltage to said body region,    wherein the potential of said drain region floats, and said substrate is connected to ground potential serving as a reference voltage.