MFOS memory transistor

Abstract

A ferroelectric transistor gate structure with a ferroelectric gate and passivation sidewalls is provided. The passivation sidewalls serve as an insulator to reduce, or eliminate, the diffusion of oxygen or hydrogen into the ferroelectric gate. A method of forming the ferroelectric gate structure is also provided. The method comprises the steps of forming a sacrificial gate structure, removing the sacrificial gate structure, depositing passivation insulator material, etching the passivation insulator material using anisotropic plasma etching to form passivation sidewalls, depositing a ferroelectric material, polishing the ferroelectric material using CMP, and forming a top electrode overlying the ferroelectric material.

What is claimed is:  
     
         1 . A ferroelectric transistor structure comprising: 
 a) a ferroelectric gate having a bottom, sides and a top overlying a semiconductor substrate;    b) a gate insulator interposed between the ferroelectric gate and the semiconductor substrate; and    c) passivation sidewalls adjacent the sides.    
     
     
         2 . The ferroelectric transistor structure of  claim 1 , wherein the semiconductor substrate is silicon or SOI.  
     
     
         3 . The ferroelectric transistor structure of  claim 1 , wherein the ferroelectric gate is PGO, PZT, SBT, SBO, SBTO, SBTN, STO, BTO, BLT, LNO or YMnO 3 .  
     
     
         4 . The ferroelectric transistor structure of  claim 1 , wherein the gate insulator is silicon nitride, nitrogen implanted silicon oxide, or silicon oxynitride.  
     
     
         5 . The ferroelectric transistor structure of  claim 1 , wherein the gate insulator is ZrO 2 , zirconium silicate, Zr—Al—Si—O, HfO 2 , hafnium silicate, Hf—Al—O, La—Al—O, lanthanum oxide or Ta 2 O 5 .  
     
     
         6 . The ferroelectric transistor structure of  claim 1 , wherein the ferroelectric gate is deposited using a chemical-solution deposition (CSD) method.  
     
     
         7 . The ferroelectric transistor structure of  claim 1 , wherein the passivation sidewalls comprise TiO 2 , Al 2 O 3 , TiAlO x , or Si 3 N 4 .  
     
     
         8 . The ferroelectric transistor structure of  claim 1 , further comprising a top electrode overlying the ferroelectric gate.  
     
     
         9 . The ferroelectric transistor structure of  claim 8 , wherein the top electrode comprises iridium, platinum, ruthenium, iridium oxide, platinum oxide, or ruthenium oxide.  
     
     
         10 . A ferroelectric transistor structure comprising a ferroelectric gate having a bottom, sides and a top, overlying a semiconductor substrate, wherein the ferroelectric gate is encapsulated by the combination of a gate insulator on the bottom, passivation sidewalls on the sides, and a top electrode on the top.  
     
     
         11 . The ferroelectric transistor structure of  claim 10 , wherein the semiconductor substrate is silicon or SOI.  
     
     
         12 . The ferroelectric transistor structure of  claim 10 , wherein the ferroelectric gate is PGO, PZT, SBT, SBO, SBTO, SBTN, STO, BTO, BLT, LNO or YMnO 3 .  
     
     
         13 . The ferroelectric transistor structure of  claim 10 , wherein the gate insulator is ZrO 2 , zirconium silicate, Zr—Al—Si—O, HfO 2 , hafnium silicate, Hf—Al—O, La—Al—O, lanthanum oxide or Ta 2 O 5    
     
     
         14 . The ferroelectric transistor structure of  claim 10 , wherein the ferroelectric gate is deposited using a chemical-solution deposition (CSD) method.  
     
     
         15 . The ferroelectric transistor structure of  claim 10 , wherein the top electrode comprises iridium, platinum, ruthenium, iridium oxide, platinum oxide, or ruthenium oxide.  
     
     
         16 . The ferroelectric transistor structure of  claim 10 , wherein the passivation sidewalls comprise TiO 2 , Al 2 O 3 , TiAlO x , or Si 3 N 4 .  
     
     
         17 . The ferroelectric transistor structure of  claim 10 , wherein the gate insulator is silicon nitride, nitrogen implanted silicon oxide, or silicon oxynitride.  
     
     
         18 . A method of forming a ferroelectric transistor structure on a substrate comprising the steps of: 
 a) forming a gate insulator over the substrate;    b) producing a sacrificial gate structure overlying the substrate;    c) removing the sacrificial gate structure;    d) depositing a passivation insulator over the substrate;    e) etching the passivation insulator using anisotropic etching, whereby passivation sidewalls are formed;    f) depositing a ferroelectric material over the substrate;    g) polishing the ferroelectric material using chemical-mechanical polishing (CMP), whereby a ferroelectric gate is formed; and    h) forming a top electrode overlying the ferroelectric gate.    
     
     
         19 . The method of  claim 18 , wherein the step of forming the sacrificial gate accomplished by the steps of: 
 a) depositing and patterning a layer of sacrificial gate material, whereby a sacrificial gate is formed;    b) forming an oxide overlying the sacrificial gate;    c) and polishing the oxide to expose the sacrificial gate.    
     
     
         20 . The method of  claim 19 , wherein the layer of sacrificial gate material is silicon nitride or polysilicon.  
     
     
         21 . The method of  claim 19 , wherein the step of polishing is accomplished using chemical-mechanical polishing (CMP).  
     
     
         22 . The method of  claim 18 , wherein the step of depositing the gate insulator is accomplished by chemical vapor deposition (CVD), pulsed CVD, sputtering, or evaporation.  
     
     
         23 . The method of  claim 18 , wherein the step of depositing the gate insulator deposits ZrO 2 , zirconium silicate, Zr—Al—Si—O, HfO 2 , hafnium silicate, Hf—Al—O, La—Al—O, lanthanum oxide or Ta 2 O 5 .  
     
     
         24 . The method of  claim 18 , wherein the step of depositing the ferroelectric material is accomplished by metal-organic chemical vapor deposition (MOCVD), or chemical-solution deposition (CSD).  
     
     
         25 . The method of  claim 18 , wherein the step of depositing the ferroelectric material deposits PGO, PZT, SBT, SBO, SBTO, SBTN, STO, BTO, BLT, LNO or YMnO 3 .  
     
     
         26 . The method of  claim 18 , wherein the top electrode is iridium, platinum, iridium oxide or platinum oxide.  
     
     
         27 . The method of  claim 18 , wherein the step of forming the top electrode is accomplished by depositing and patterning a top electrode layer.  
     
     
         28 . The method of  claim 18 , wherein the step of forming the top electrode is accomplished by using a damascene process.  
     
     
         29 . The method of  claim 18 , wherein the step of depositing the passivation insulator deposits TiO 2 , Al 2 O 3 , TiAlO x , or Si 3 N 4 .  
     
     
         30 . The method of  claim 18 , wherein the step of etching the passivation insulator is accomplished using anisotropic plasma etch.