Semiconductor integrated circuit device allowing accurate evaluation of access time of memory core contained therein and access time evaluating method

Abstract

An external clock signal is transmitted as a clock signal to a memory core through a first signal transmitting path. In response to activation of the clock signal CLK, memory core starts a read operation. Read data output from memory core is latched by a latch circuit. An external signal designating a latch timing is transmitted as a latch timing signal to the latch circuit through a second signal transmitting path. A delay circuit is provided in at least one of the first and second signal transmitting paths, so that the first and second signal transmitting paths come to have the same signal delay.

What is claimed is:  
     
         1 . A semiconductor integrated circuit device, comprising: 
 a memory circuit executing a read operation in which a plurality of data are output in parallel, at least one of said plurality of data being transmitted to an internal node;    a first signal transmitting path transmitting a control signal designating start of said read operation to said memory circuit;    a first data latch circuit responsive to a test timing signal activated after a prescribed time period from activation of said control signal, for taking in and holding a signal level of said internal node;    a second signal transmitting path transmitting said test timing signal to said first data latch circuit; and    a signal delay circuit arranged in at least one of said first and second signal transmitting paths so as to align signal propagation delays in said first and second signal transmitting circuits.    
     
     
         2 . The semiconductor integrated circuit device according to  claim 1 , wherein 
 said at least one of said plurality of data is determined in accordance with expected time necessary for said read operation based on a layout design of said memory circuit, for each of said plurality of data.    
     
     
         3 . The semiconductor integrated circuit device according to  claim 1 , further comprising second to Nth data latch circuits responsive to said test timing signals received from said second signal transmitting circuit, for taking in and holding other (N−1) (N: natural number not smaller than 2) data of said plurality of data.  
     
     
         4 . The semiconductor integrated circuit device according to  claim 3 , wherein 
 N is 2; and    one and another one of said plurality of data are determined in accordance with expected time necessary for said read operation based on a layout design of said memory circuit for each of said plurality of data.    
     
     
         5 . The semiconductor integrated circuit device according to  claim 3 , further comprising a data comparing circuit for comparing result of comparison between each of said plurality of data held in said first to Nth data latch circuits.  
     
     
         6 . The semiconductor integrated circuit device according to  claim 5 , wherein 
 N=2: and    one and another one of said plurality of data are determined in accordance with expected time necessary for said read operation based on a layout design of said memory circuit for each of said plurality of data.    
     
     
         7 . The semiconductor integrated circuit device according to  claim 1 , further comprising 
 a data comparing circuit arranged between said memory circuit and said first data latch circuit, for outputting, to said internal node, result of comparison between one and other M (M: natural number) of said plurality of data lines.    
     
     
         8 . The semiconductor integrated circuit device according to  claim 7 , wherein 
 M is 1; and    one and another one of said plurality of data are determined in accordance with an expected time necessary for said read operation based on a layout design of said memory circuit, for each of said plurality of data.    
     
     
         9 . The semiconductor integrated circuit device according to  claim 1 , wherein 
 said prescribed time period is set in accordance with a standard value of an access time of said memory circuit.    
     
     
         10 . A semiconductor integrated circuit device, comprising: 
 a memory circuit executing a read operation in which a plurality of data are output in parallel;    a signal transmitting path transmitting to said memory circuit a control signal for designating start of said read operation;    a delay circuit receiving said control signal from said signal transmitting path and generating an internal timing signal by delaying said control signal; and    a data latch circuit responsive to said internal timing signal for taking in and holding at least one of said plurality of data.    
     
     
         11 . The semiconductor integrated circuit device according to  claim 10 , wherein 
 delay time of said delay circuit is set based on a standard value of an access time of said memory circuit.    
     
     
         12 . The semiconductor integrated circuit device according to  claim 10 , wherein 
 delay time of said delay circuit is set in accordance with an external control signal.    
     
     
         13 . A method of evaluating access time of a memory circuit contained in a semiconductor integrated circuit device, comprising the steps of: 
 activating a control signal designating a start of a read operation in which a plurality of data are output in parallel, to said memory circuit;    transmitting activated said control signal to said memory circuit;    after a prescribed time period from activation of said control signal, activating a test timing signal in response to a signal activated independent from said control signal;    transmitting activated said test timing signal to a latch circuit;    taking and holding, by said latch circuit, at least one of said plurality of data output from said memory circuit, in response to activation of the transmitted said test timing signal; and    further delaying at least one of said control signal and said test timing signal, and transmitting to at least corresponding one of said memory circuit and said latch circuit.    
     
     
         14 . The method of evaluating access time according to  claim 13 , wherein 
 said latch circuit holds a part of said plurality of data;    said method further comprising the step of outputting results of comparison between each of said part of data held by said latch circuit.    
     
     
         15 . The method of evaluating access time according to  claim 13 , wherein 
 said prescribed time period is set in accordance with a standard value of an access time of said memory circuit.