Semiconductor device and method of manufacturing the same

Abstract

Sides of via hole do not bow horizontally, thereby preventing an increase of a resistance of a wiring layer connected to a conductor in the via hole. A semiconductor device comprises a first wiring layer, an insulating layer over the first wiring, a second wiring on the insulating layer, a first hole formed in the first wiring, a second hole formed in the insulating layer connecting with at least a part of the first hole, and a conductive material in first and second holes that electrically connects the first wiring layer to the second wiring layer.

What is claimed is:  
     
         1 . A method of manufacturing a semiconductor device comprising: 
 forming a first wiring layer;    forming a first hole in said first wiring layer;    forming an insulating layer on said wiring layer and in said first hole;    forming a second hole in said insulating layer, said second hole exposing at least a part of an inner side surface of said first hole;    filling said second hole with a conductive material.    
     
     
         2 . The method as claimed in  claim 1 , wherein said insulating layer is completely removed from said first hole when said second hole is formed.  
     
     
         3 . The method as claimed in  claim 1 , wherein said insulating layer remains in a part of said first hole when said second hole is formed.  
     
     
         4 . The method as claimed in  claim 1 , wherein a cross-sectional area of said first hole is smaller than that of an upper portion of said second hole.  
     
     
         5 . The method as claimed in  claim 1 , wherein said insulating layer comprises a low dielectric film.  
     
     
         6 . The method as claimed in  claim 5 , wherein said low dielectric film is HSQ.  
     
     
         7 . The method as claimed in  claim 5 , wherein said insulating layer further comprises an insulating film on said low dielectric film, said insulating film having an etching rate that is lower than an etching rate of said low dielectric film,.  
     
     
         8 . The method as claimed in  claim 1 , wherein said insulating layer is an application film.  
     
     
         9 . The method as claimed in  claim 1 , wherein a width of said first wiring layer is greater than 250 μm.  
     
     
         10 . The method as claimed in  claim 1 , further comprising forming a second wiring layer on said insulating layer, wherein said conductive material electrically connects said second wiring layer to said first wiring layer.  
     
     
         11 . The method as claimed in  claim 1 , wherein said first hole has a depth that avoids horizontal over-etching of said insulating layer above said first hole when forming said second hole.  
     
     
         12 . A method of avoiding over-etching of an insulator layer, comprising: 
 forming a first horizontal wiring layer;    forming a first hole in said first wiring layer;    forming an insulating layer on said wiring layer and in said first hole;    etching a second hole in said insulating layer, said second hole exposing at least a part of an inner side surface of said first hole;    said first hole having a depth that avoids horizontal over-etching of said insulating layer above said first hole when forming said second hole; and    filling said second hole with a conductive material.    
     
     
         13 . The method as claimed in  claim 12 , wherein said first hole extends completely through said first wiring layer.