Method for manufacturing a semiconductor device

Abstract

A method for manufacturing a semiconductor device incorporating therein an insulating layer prevents a bridge between metal patterns. The method begins with the preparation a semiconductor substrate divided into a peripheral region and a cell region provided with a first metal pattern formed thereon, wherein the regions are adjacent to each other. Thereafter, a first insulating layer is covered on top of the first metal pattern. And then, a second insulating layer is formed on top of the first insulating layer, wherein an etching rate of the first insulating layer is slower than that of the second insulating layer. In the next step, the second insulating layer is planarized to a predetermined thickness for smoothing a step contour between the cell region and the peripheral region. Finally, a second metal pattern is formed on top of the planarized second insulating layer, thereby preventing a bridge between the first and the second metal patterns.

What is claimed is:  
     
         1 . A semiconductor device provided with a peripheral region and a cell region formed thereon a three-dimensional capacitor comprising; 
 a upper electrode of the three-dimensional capacitor;    a metal patterned layer;    a first insulating layer formed on top of the upper electrode; and    a second insulating layer formed between the first insulating layer and the metal patterned layer, wherein an etching rate of the first insulating layer is slower than that of the second insulating layer.    
     
     
         2 . The semiconductor device as recited in  claim 1 , wherein the three-dimensional capacitor is in the form of a cylinder.  
     
     
         3 . The semiconductor device as recited in  claim 2 , wherein the metal patterned layer is a redundancy word line.  
     
     
         4 . The semiconductor device as recited in  claim 3 , wherein the second insulating layer is made of a BPSG and the first insulating layer is made of an MTO.