Variable threshold voltage double gated transistors and method of fabrication

Abstract

The present invention provides a double gate transistor and a method for forming the same that facilitates the formation of different transistors having different threshold voltages. The embodiments of the present invention form transistors having different body widths. By forming double gate transistors with different body widths, the preferred embodiment forms double gate transistors that have different threshold voltages, without adding excessive process complexity. The preferred embodiment of the present invention is implemented using a fin type double gated structure. In a fin type structure, the double gates are formed on each side of the body, with the body being disposed horizontally between the gates.

1 . A method for forming a plurality of transistors having different threshold voltages, the method comprising the steps of: 
 a) providing a semiconductor substrate;    b) forming a plurality of shapes on the semiconductor substrate, each of the plurality of shapes having a width;    c) selectively adjusting the widths of at least one selected shapes;    d) patterning the semiconductor substrate using the plurality of shapes to form a plurality of transistor bodies such that the width of each the plurality of transistor bodies is at least partially determined by the width of a corresponding one of the plurality of shapes;    e) providing a first gate structure of a first work-function adjacent a first body edge of each of the plurality of transistor bodies; and    f) providing a second gate structure of a second work-function adjacent a second body edge of each of the plurality of transistor bodies.    
     
     
         2 . The method of  claim 1  wherein the first gate structure of a first work-function comprises p-type material and wherein the second gate structure of a second work-function comprises n-type material.  
     
     
         3 . The method of  claim 1  further comprising (g) forming source, drain, and halo regions utilizing angled implantation..  
     
     
         4 . The method of  claim 1  wherein the semiconductor substrate comprises a silicon-on-insulator layer, and wherein the step of patterning the semiconductor substrate using the plurality of shapes to form a plurality of transistor bodies comprises patterning the silicon-on-insulator layer.  
     
     
         5 . The method of  claim 3 , wherein said substrate has a horizontal plane, and wherein source and drain regions are formed therein at an angle between approximately 70° and 83° with respect to said horizontal plane.  
     
     
         6 . The method of  claim 1  wherein the step of forming a plurality of shapes and the step of patterning the semiconductor substrate using the plurality of shapes to form a plurality of transistor bodies comprises: forming a mandrel layer on the semiconductor substrate; patterning the mandrel layer to form an exposed side, and forming a sidewall spacer adjacent to the exposed side, and wherein a first edge of the sidewall spacer defines the first body edge and a second edge of the sidewall spacer defines the second body edge.  
     
     
         7 . The method of  claim 1  wherein the step of forming a plurality of shapes and the step of patterning the semiconductor substrate using the plurality of shapes to form a plurality of transistor bodies comprises forming a mandrel layer on the semiconductor substrate, patterning the mandrel layer, and using the patterned mandrel layer to define the first body edge, forming a sidewall spacer adjacent to a gate material layer and using the sidewall spacer to define the second body edge.  
     
     
         8 . A method for forming a plurality of field effect transistors having different threshold voltages, the method comprising the steps of: 
 a) providing a silicon-on-insulator substrate, the silicon-on-insulator substrate comprising a silicon layer on a buried dielectric layer;    b) forming a mandrel layer on the silicon layer; patterning the mandrel layer to define a plurality of mandrel layer edges;    c) patterning the silicon layer with the plurality of mandrel layer edges, the patterning of the silicon layer providing a plurality of first body edges;    d) forming a plurality of first gate dielectrics on the plurality of first body edges;    e) providing a plurality of first gate structures of a first work-function adjacent the first body edges on the plurality of first gate dielectrics;    f) patterning the mandrel layer to expose a first edges of the plurality of first gate structures;    g) forming a plurality of sidewall spacers adjacent the first edges of the plurality of first gate structures, the sidewall spacers having a sidewall spacer width;    h) adjusting the width of selected sidewall spacers;    i) patterning the silicon layer with plurality of sidewall spacers, the pattering of the silicon layer providing a plurality of second body edges, where the first and second body edges of the patterned silicon layer define a plurality of transistor bodies;    j) providing a plurality of second gate dielectrics on the plurality of second body edges; and    k) providing a plurality of second gate structures of a second work-function adjacent the second body edges on the plurality of second gate dielectrics.    
     
     
         9 . The method of  claim 8  wherein the plurality of first gate structures of a first work-function comprises p-type polysilicon material and wherein the plurality of second gate structures of a second work-function comprises n-type polysilicon material.  
     
     
         10 . The method of  claim 8  wherein the plurality of first gate structures of a first work-function comprises n-type polysilicon material and wherein the plurality of second gate structures of a second work-function comprises p-type polysilicon material.  
     
     
         11 . The method of  claim 8  further comprising the step of forming a plurality of source/drain implants into the bodies of the transistors by performing an angled implant into the transistor bodies.  
     
     
         12 . A plurality of transistors comprising: 
 a) a plurality of transistor bodies formed on a substrate, the transistor bodies each having a first vertical edge and a second vertical edge defining a transistor body width, wherein a selected portion of the plurality of transistor bodies has an adjusted width;    b) a plurality of first gate structures, each of the plurality of first gate structures adjacent to one of the plurality of transistor body first vertical edges, the plurality of first gate structures having a first work-function; and    c) a plurality of second gate structures, each of the plurality of second gate structures adjacent to one of the plurality of transistor body second vertical edges, the plurality of second gate structures having a second work-function.    
     
     
         13 . The transistors of  claim 12  wherein the plurality of first gate structures comprise p-type material and wherein the plurality of second gate structures comprise n-type material.  
     
     
         14 . The transistors of  claim 12  wherein the plurality of transistor bodies comprise semiconductor fins.  
     
     
         15 . The transistors of  claim 12  wherein the plurality of transistor bodies comprise a portion of a silicon-on-insulator layer.  
     
     
         16 . The transistors of  claim 12  wherein the plurality of first and second gate structures comprise polysilicon.  
     
     
         17 . The transistors of  claim 12  further comprising a plurality of first gate dielectrics between the transistor body first edges and the first gate structures and a plurality of second gate dielectrics between the transistor body second edges and the second gate structures.  
     
     
         18 . The transistors of  claim 12  wherein the plurality of transistor fins comprise source/drain implants.  
     
     
         19 . The transistors of  claim 12  wherein each of said first and second plurality of gate structures has a length, and wherein said width of each of said plurality of transistor bodies is less than approximately one quarter of said length.  
     
     
         20 . The transistors of  claim 12 , wherein said width of said plurality of transistor bodes is greater than approximately 2.5 nm  
     
     
         21 . A plurality of dual gate transistors, comprising a first transistor having a first body width, a first gate, a second gate; and a second transistor having a second body width, a first gate, and a second gate, wherein each of said first gates have a first work-function and each of said second gates have a second work-function.