Method of ion implantation for achieving desired dopant concentration

Abstract

A method for forming a plurality of MOSFETs wherein each one of the MOSFET has a unique predetermined threshold voltage. A doped well or tub is formed for each MOSFET. A patterned mask is then used to form a material line proximate each semiconductor well, wherein the width of the line is dependent upon the desired threshold voltage for the MOSFET. A tilted ion implantation is performed at an acute angle with respect to the substrate surface such that the ion beam passes through the material line. Thicker lines have a lower transmission coefficient for the ion beam and thus the intensity of the ion beam reaching the adjacent semiconductor well is reduced. By appropriate selection of the line width the dopant density in the well, and thus the final MOSFET threshold voltage, is controllable.

What is claimed is:  
     
         1 . A method for fabricating a semiconductor device region comprising: 
 forming a doped semiconductor region on a semiconductor layer;    forming a first material line proximate the doped semiconductor region on the top surface of the semiconductor layer;    performing a first tilted ion implantation through the first material line, wherein the ion beam intersects the first material line at an angle with respect to the top surface of the semiconductor layer such that the ion beam passes through the first material line prior to striking the doped semiconductor region, and wherein the implanted ion dosage reaching the doped semiconductor region to increase the dopant concentration thereof is dependent on the material line width.    
     
     
         2 . The method of  claim 1  wherein the step of forming the material line comprises forming a first layer over the semiconductor layer, patterning the first layer to identify the location of the material line, and removing the material of the first layer except for the material line.  
     
     
         3 . The method of  claim 1  wherein the material of the first material line is selected from among silicon nitride, silicon dioxide, photo resist and polycrystalline silicon.  
     
     
         4 . The method of  claim 1  wherein the tilt angle is in the range of about 1 to 89 degrees.  
     
     
         5 . The method of  claim 1  wherein the width of the material line is selected to control the ion implantation dosage reaching the doped semiconductor region.  
     
     
         6 . The method of  claim 1  wherein the height of the material line is selected to control the ion implantation dosage reaching the doped semiconductor region.  
     
     
         7 . The method of  claim 1  further comprising: 
 forming a second material line proximate the doped semiconductor region on the opposing side of the doped semiconductor region from the first material line;  
 performing a second tilted ion implantation through the second material line, wherein the ion beam intersects the second material line at an angle with respect to the top surface of the semiconductor layer such that the ion beam passes through the second material line prior to striking the doped semiconductor region.  
 
     
     
         8 . The method of  claim 7  wherein after the first and the second tilted ion implantations the lateral dopant concentration in the doped semiconductor region is substantially uniform.  
     
     
         9 . The method of  claim 1  wherein the dopant concentration is laterally non-uniform.  
     
     
         10 . A method of doping a semiconductor device region comprising: 
 forming a plurality of doped semiconductor regions on a semiconductor layer by one or more dopant introduction steps, wherein at least one doped semiconductor region is associated with one of a plurality of semiconductor devices;    forming a material line proximate at least one of the plurality of semiconductor regions;    performing an ion implantation wherein the ion beam intersects the material line at an angle with respect to the top surface of the semiconductor layer such that the ion beam passes through the material line prior to striking the proximate semiconductor region, and wherein the implanted ions further increase the doping concentration of the doped semiconductor region, as determined by the width of the material line.    
     
     
         11 . The method of  claim 10  wherein the doped semiconductor region is a semiconductor well.  
     
     
         12 . The method of  claim 10  wherein the material of the material line is selected from among silicon nitride, silicon dioxide, photo resist and polycrystalline silicon.  
     
     
         13 . The method of  claim 10  further comprising: 
 forming an opposing material line proximate and on the opposing side of the doped semiconductor region from the material line; and  
 performing a second tilted ion implantation through the opposing material line, wherein the ion beam intersects the opposing material line at an angle with respect to the top surface of the semiconductor layer such that the ion beam passes through the opposing material line prior to striking the doped semiconductor region.  
 
     
     
         14 . The method of  claim 10  wherein a plurality of material lines are formed, wherein the width and the height of each material line is selected to achieve the desired doping concentration in the doped semiconductor region.  
     
     
         15 . A method for fabricating a plurality of field effect transistors, comprising: 
 forming a plurality of doped semiconductor wells on a semiconductor substrate, wherein each doped semiconductor well is associated with a field-effect transistor;    forming a plurality of material lines each proximate a doped semiconductor well, wherein each one of the plurality of material lines has a predetermined width;    performing a tilted ion implantation through each one of the material lines such that the ion beam intersects each one of the plurality of the material lines at an acute angle with respect to the top surface of the semiconductor layer and strikes the proximate doped semiconductor well, and wherein the implanted ions further increase the doping concentration of the doped semiconductor well;    in each of the plurality of semiconductor wells, forming an oxide layer on a region of the semiconductor layer, wherein the region below the oxide layer defines a channel region;    forming a gate region over the oxide layer in each one of the plurality of semiconductor wells; and    forming a source region and a drain region in each one of the plurality of doped semiconductor wells with the channel region therebetween;    wherein the combination of a source region, a drain region and a gate associated with each one of the plurality of doped semiconductor wells forms a field-effect transistor, and wherein the dopant density of the channel region is dependent on the transmission of ions through the material line, and wherein the threshold voltage of each field-effect transistor of the plurality of field-effect transistors is dependent on the dopant density.    
     
     
         16 . The method of  claim 15  wherein after the step of forming the doped semiconductor wells, the doped semiconductor wells have a minimal dopant density.  
     
     
         17 . The method of  claim 15  wherein the transmissive properties of each material line are a function of the material line width.  
     
     
         18 . The method of  claim 15  wherein the material line comprises silicon nitride, silicon dioxide, photo resist or polycrystalline silicon.  
     
     
         19 . The method of  claim 15  further comprising: 
 forming an opposing material line proximate and on the opposing side of the doped semiconductor well from the material line; and  
 performing a second tilted ion implantation through the opposing material line, wherein the ion beam intersects the opposing material line at an angle with respect to the top surface of the semiconductor layer such that the ion beam passes through the opposing material line prior to striking the doped semiconductor well.  
 
     
     
         20 . The method of  claim 15  wherein the width and the height of each one of the plurality of material lines is selected to achieve the desired threshold voltage for the associated field-effect transistor.  
     
     
         21 . A semiconductor device comprising a plurality of field effect transistors, wherein a first of the transistors is formed in a tub region of a first conductivity type, characterized by a threshold voltage different from that of a second of the transistors, the first transistor including a gate structure and first and second source/drain regions of a net conductivity of a second conductivity type formed in the tub region, each source/drain region formed along a lateral surface region of the device on an opposing side of the gate region, each source/drain region including a first portion extending toward the gate region and a second portion extending away from the gate region, one of the source drain regions characterized by a tub dopant concentration of the first conductivity type along the lateral surface region with a relatively high first tub dopant concentration in the second portion and a relatively low tub dopant concentration extending from between the second portion and the first portion toward the gate structure.  
     
     
         22 . The device of  claim 21  wherein the relatively low tub dopant concentration in said one source/drain region extends to the gate structure.  
     
     
         23 . The device of  claim 21  wherein the relatively high tub dopant concentration in said one source/drain region is less than 1E19 per cm 3  and the relatively low dopant concentration in said one source/drain region is less than 9E18 per cm 3 .  
     
     
         24 . The device of  claim 21  wherein the relatively high tub dopant concentration in said one source/drain region is between 1E16 per cm 3  and 1E19 per cm 3  and the relatively low dopant concentration in said one source/drain region is less than 9E18 per cm 3 .  
     
     
         25 . The device of  claim 21  wherein the relatively high tub dopant concentration in said one source/drain region is approximately 2E18 per cm 3  and the relatively low dopant concentration in said one source/drain region is approximately 1E18 per cm 3 .  
     
     
         26 . A semiconductor device comprising a plurality of field effect transistors wherein a first of the transistors is formed in a tub region of first conductivity type, the first transistor including a gate structure and first and second source/drain regions of a net conductivity of a second conductivity type formed in the tub region, the tub region below one source/drain region including a first portion extending along the one source/drain region toward the gate region and a second portion extending along the one source/drain region away from the gate region, the first portion characterized by a low tub dopant concentration of the first conductivity type relative to the second portion tub dopant concentration.  
     
     
         27 . The device of  claim 26  wherein the low first portion tub dopant concentration extends to below the gate structure.  
     
     
         28 . The device of  claim 26  wherein the tub dopant concentration in the second portion is less than 1E19 per cm 3  and the tub dopant concentration in the first portion is less than 9E18 per cm 3 .  
     
     
         29 . The device of  claim 26  wherein the tub dopant concentration in the second portion is between 1E16 per cm 3  and 1E19 per cm 3  and the tub dopant concentration in the first portion is less than 9E18 per cm 3 .  
     
     
         30 . The device of  claim 26  wherein the tub dopant concentration in the second portion is approximately 1E18 per cm 3  and the tub dopant concentration in the first portion is approximately 5E17 per cm 3 .