Panel stacking of BGA devices to form three-dimensional modules

Abstract

A chip stack comprising at least two base layers, each of which includes a base substrate and a first conductive pattern disposed on the base substrate. The chip stack further comprises at least one interconnect frame having a second conductive pattern disposed thereon. The interconnect frame is disposed between the base layers, with the second conductive pattern being electrically connected to the first conductive pattern of each of the base layers. Also included in the chip stack are at least two integrated circuit chips which are electrically connected to respective ones of the first conductive patterns. One of the integrated circuit chips is at least partially circumvented by the interconnect frame and at least partially covered by one of the base layers. The chip stack further comprises a transposer layer comprising a transposer substrate having a third conductive pattern disposed thereon. The first conductive pattern of one of the base layers is electrically connected to the third conductive pattern of the transposer layer.

1 . A chip stack comprising: 
 at least two base layers, each of the base layers comprising: 
 a base substrate; and  
 a first conductive pattern disposed on the base substrate;  
   a least one interconnect frame having a second conductive pattern disposed thereon, the interconnect frame being disposed between the base layers, with the second conductive pattern being electrically connected to the first conductive pattern of each of the base layers; and    at least two integrated circuit chips electrically connected to respective ones of the first conductive patterns, one of the integrated circuit chips being at least partially circumvented by the interconnect frame and at least partially covered by one of the base layers.    
     
     
         2 . A chip stack of  claim 1  further comprising: 
 a transposer layer comprising: 
 a transposer substrate; and  
 a third conductive pattern disposed on the transposer substrate;  
 
 the first conductive pattern of one of the base layers being electrically connected to the third conductive pattern.  
 
     
     
         3 . The chip stack of  claim 2  wherein: 
 the base substrate defines opposed top and bottom surfaces; and  
 the first conductive pattern comprises: 
 a first set of base pads disposed on the top surface of the base substrate;  
 a second set of base pads disposed on the top surface of the base substrate and electrically connected to respective ones of the base pads of the first set; and  
 a third set of base pads disposed on the bottom surface of the base substrate and electrically connected to respective ones of the base pads of the second set;  
 
 the integrated circuit chips being disposed upon respective ones of the top surfaces of the base substrates and electrically connected to at least some of the base pads of respective ones of the first sets, with the base pads of the second set of one of the base layers being electrically connected to the second conductive pattern, and the base pads of the third set of one of the base layers being electrically connected to the second conductive pattern.  
 
     
     
         4 . The chip stack of  claim 3  wherein: 
 the interconnect frame defines opposed top and bottom surfaces; and  
 the second conductive pattern comprises: 
 a first set of frame pads disposed on the top surface of the interconnect frame; and  
 a second set of frame pads disposed on the bottom surface of the interconnect frame and electrically connected to respective ones of the frame pads of the first set;  
 
 the interconnect frame being disposed between the base layers such that the frame pads of the second set are electrically connected to respective ones of the base pads of the second set of one of the base layers, and the frame pads of the first set are electrically connected to respective ones of the base pads of the third set of one of the base layers.  
 
     
     
         5 . The chip stack of  claim 4  wherein: 
 the transposer substrate defines opposed top and bottom surfaces; and  
 the third conductive pattern comprises: 
 a first set of transposer pads disposed on the top surface of the transposer substrate; and  
 a second set of transposer pads disposed on the bottom surface of the transposer substrate and electrically connected to respective ones of the transposer pads of the first set;  
 
 the base pads of the third set of one of the base layers being electrically connected to respective ones of the transposer pads of the first set.  
 
     
     
         6 . The chip stack of  claim 5  wherein the transposer pads of the first set, the frame pads of the first and second sets, and the base pads of the second and third sets are arranged in identical patterns.  
     
     
         7 . The chip stack of  claim 6  wherein: 
 the transposer and base substrates each have a generally rectangular configuration defining opposed pairs of longitudinal and lateral peripheral edge segments;  
 the interconnect frame has a generally rectangular configuration defining opposed pairs of longitudinal and lateral side sections;  
 the transposer pads of the first set extend along the longitudinal and lateral peripheral edge segments of the transposer substrate;  
 the first and second sets of frame pads extend along the longitudinal and lateral side sections of the interconnect frame; and  
 the second and third sets of base pads extend along the longitudinal and lateral peripheral edge segments of the base substrate.  
 
     
     
         8 . The chip stack of  claim 6  wherein each of the transposer pads of the second set has a generally spherical configuration.  
     
     
         9 . The chip stack of  claim 6  wherein each of the transposer pads of the first set and each of the frame pads of the first and second sets has a generally semi-spherical configuration.  
     
     
         10 . The chip stack of  claim 6  wherein: 
 each of the frame pads of the first set is electrically connected to a respective one of the frame pads of the second set via a frame feed-through hole; and  
 each of the base pads of the second set is electrically connected to a respective one of the base pads of the third set via a base feed-through hole.  
 
     
     
         11 . The chip stack of  claim 10  wherein each of the frame and base feed-through holes is plugged with a conductive material.  
     
     
         12 . The chip stack of  claim 11  wherein the conductive material is selected from the group consisting of: 
 nickel;  
 gold;  
 tin;  
 silver epoxy; and  
 combinations thereof.  
 
     
     
         13 . The chip stack of  claim 6  wherein the integrated circuit chips each comprise: 
 a body having opposed, generally planar top and bottom surfaces; and  
 a plurality of conductive contacts disposed on the bottom surface of the body;  
 the conductive contacts of each of the integrated circuit chips being electrically connected to respective ones of the base pads of the first set of a respective one of the first conductive patterns.  
 
     
     
         14 . The chip stack of  claim 13  wherein the transposer pads of the second set, the base pads of the first set, and the conductive contacts are arranged in identical patterns.  
     
     
         15 . The chip stack of  claim 13  further comprising a layer of flux/underfill disposed between the bottom surface of the body of each of the integrated circuit chips and respective ones of the top surfaces of the base substrates.  
     
     
         16 . The chip stack of  claim 13  wherein the body of each of the integrated circuit chips and the interconnect frame are sized relative to each other such that the top surface of the body of the integrated circuit chip at least partially circumvented by the interconnect frame does not protrude beyond the top surface thereof.  
     
     
         17 . The chip stack of  claim 13  wherein the integrated circuit chips are each selected from the group consisting of: 
 a BGA device;  
 a fine pitch BGA device;  
 a CSP device; and  
 a flip chip device.  
 
     
     
         18 . The chip stack of  claim 2  wherein the transposer and base substrates are each fabricated from a polyamide.  
     
     
         19 . The chip stack of  claim 1  further comprising: 
 a second interconnect frame, the second conductive pattern of which is electrically connected to the first conductive pattern of one of the base layers such that the second interconnect frame at least partially circumvents one the integrated circuit chips;  
 a third base layer, the first conductive pattern of which is electrically connected to the second conductive pattern of the second interconnect frame such that the third base layer at least partially covers one of the integrated circuit chips; and  
 a third integrated circuit chip electrically connected to the first conductive pattern of the third base layer.  
 
     
     
         20 . The chip stack of  claim 19  further comprising: 
 a multiplicity of additional interconnect frames, base layers, and integrated circuit chips;  
 the second conductive pattern of each of the interconnect frames being electrically connected to the first conductive patterns of any adjacent pair of base layers, with each of the integrated circuit chips being electrically connected to the first conductive pattern of a respective one of the base layers.  
 
     
     
         21 . A method of assembling a chip stack, comprising the steps of: 
 (a) electrically connecting an integrated circuit chip to a first conductive pattern of a base layer;    (b) electrically connecting a second conductive pattern of an interconnect frame to the first conductive pattern such the interconnect frame at least partially circumvents the integrated circuit chip;    (c) electrically connecting another integrated circuit chip to the first conductive pattern of another base layer; and    (d) electrically connecting the first conductive pattern of one of the base layers to the second conductive pattern of the interconnect frame such that one of the integrated circuit chips is disposed between the base layers.    
     
     
         22 . The method of  claim 21  further comprising the step of: 
 (e) electrically connecting the first conductive pattern of one of the base layers to a third conductive pattern of a transposer layer.  
 
     
     
         23 . The method of  claim 21  wherein steps (a) and (c) each comprise applying a layer of flux/underfill to each of the base layers over portions of the first conductive patterns prior to the electrical connection of respective ones of the integrated circuit chips thereto.  
     
     
         24 . The method of  claim 22  wherein steps (a)-(e) are accomplished via soldering.  
     
     
         25 . A method of assembling a chip stack, comprising the steps of: 
 (a) providing a transposer panel which has opposed surfaces and a plurality of conductive pads disposed on the opposed surfaces thereof;    (b) providing at least two base panels which each have opposed surfaces and a plurality of conductive pads disposed on the opposed surfaces thereof;    (c) providing at least one frame panel which has opposed surfaces and a plurality of conductive pads disposed on the opposed surfaces thereof;    (d) providing a plurality of integrated circuit chips which each have opposed sides and a plurality of conductive contacts disposed on one of the sides thereof;    (e) placing integrated circuit chips upon each of the base panels such that the conductive contacts of each of the integrated circuit chips are disposed on at least some of the conductive pads of respective ones of the base panels;    (f) stacking one of the base panels upon the transposer panel such that at least some of the conductive pads of the base panel are disposed on at least some of the conductive pads of the transposer panel;    (g) stacking the frame panel upon the base panel such that at least some of the conductive pads of the frame panel are disposed on at least some of the conductive pads of the base panel; and    (h) stacking another base panel upon the frame panel such that at least some of the conductive pads of the base panel are disposed on at least some of the conductive pads of the frame panel.    
     
     
         26 . The method of  claim 25  wherein steps (g) and (h) are repeated at least once subsequent to step (h).  
     
     
         27 . The method of  claim 25  further comprising the step of: 
 (i) bonding the conductive contacts of the integrated circuit chips to at least some of the conductive pads of the base panel upon which the integrated circuit chips are positioned, bonding at least some of the conductive pads of one of the base panels to at least some of the conductive pads of the transposer panel, and bonding at least some of the conductive pads of the frame panel to at least some of the conductive pads of each of the base panels.  
 
     
     
         28 . The method of  claim 25  wherein at least three spacer sheets are also provided which each have opposed surfaces and a plurality of openings disposed therein, and: 
 step (f) comprises stacking one of the spacer sheets upon the transposer panel and stacking the base panel upon the spacer sheet such that the conductive pads of the transposer and base panels are aligned with respective ones of the openings;  
 step (g) comprises stacking another spacer sheet upon the base panel and stacking the frame panel upon the spacer sheet such that the conductive pads of the base and frame panels are aligned with respective ones of the openings; and  
 step (h) comprises stacking another spacer sheet upon the frame panel and stacking the base panel upon the spacer sheet such that the conductive pads of the frame and base panels are aligned with respective ones of the openings.