US2003048388A1PendingUtilityA1
System for receiving transport streams
Priority: Apr 12, 2001Filed: Apr 11, 2002Published: Mar 13, 2003
Est. expiryApr 12, 2021(expired)· nominal 20-yr term from priority
H04N 21/42661H04N 21/42646H04N 21/42692H04N 21/434H04N 21/44004H04N 21/4383H04N 21/42669
43
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Claims
Abstract
A system comprising first input means for receiving a transport stream from an external source, second input means for receiving an input from a memory, means for connecting the first and second input means to an interface which is arranged to provide an output stream to a decoder. The second input means is arranged to provide an output to the interface in such a form that the interface does not distinguish between the output from the first and second input means.
Claims
exact text as granted — not AI-modified1 . A system comprising first input means for receiving a transport stream from an external source, second input means for receiving an input from a memory, means for connecting the first and second input means to an interface which is arranged to provide an output stream to a decoder, wherein the second input means is arranged to provide an output to the interface in such a form that the interface does not distinguish between the output from the first and second input means.
2 . A system as claimed in claim 1 , wherein said input from memory comprises a transport stream.
3 . A system as claimed in claim 1 , wherein said second input means comprises a buffer.
4 . A system as claimed in claim 3 , wherein said buffer comprises a FIFO.
5 . A system as claimed in claim 3 , wherein half the size of the buffer equals a bit rate of the input to the second input means multiplied by the time taken to read data from the memory and write it to the second input.
6 . A system as claimed in claim 1 , wherein a register is provided in said second input means to convert a serial stream of data into a parallel stream of data.
7 . A system as claimed in claim 1 , wherein said memory is external to said system.
8 . A system as claimed in claim 1 , wherein said memory is in said system.
9 . A system as claimed in claim 1 , wherein said memory comprises one or more of the following:
CD-ROM, hard disk, floppy disk, CPU, and RAM.
10 . A system as claimed in claim 1 , wherein said first input means is arranged to receive a transport stream from a cable or satellite link.
11 . A system as claimed in claim 1 , wherein said second input means comprises clock means, said clock means providing a clock signal for controlling the output of said input to said second input.
12 . A system as claimed in claim 1 , wherein said second input is arranged to output valid data only.
13 . An integrated circuit comprising first input means for receiving a transport stream from an external source, second input means for receiving an input from a memory, means for connecting the first and second input means to an interface which is arranged to provide an output stream to a decoder, wherein the second input means is arranged to provide an output to the interface in such a form that the interface does not distinguish between the output from the first and second input means.
14 . A set top box comprising first input means for receiving a transport stream from an external source, second input means for receiving an input from a memory, means for connecting the first and second input means to an interface which is arranged to provide an output stream to a decoder, wherein the second input means is arranged to provide an output to the interface in such a form that the interface does not distinguish between the output from the first and second input means.Join the waitlist — get patent alerts
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