Integrated circuit and method of adjusting capacitance of a node of an integrated circuit

Abstract

The present invention relates to an integrated circuit device and method of adjusting capacitance of a node of an integrated circuit In one embodiment, the device comprises a first digital input, a first parasitic capacitance block, a first output, a second digital input, a second parasitic capacitance block and a second output. The first parasitic capacitance block includes an inverter, a variable capacitance element, and a wire capacitance element. The first parasitic capacitance block has a capacitance that is a function of the first digital input. The first output is responsive to the first parasitic capacitance block, and the second output is responsive to the second parasitic capacitance block. In a particular embodiment, the method includes selecting a logic state of a digital input; applying the digital input to a parasitic capacitance block having an output, the output having a first capacitance when the digital input is in first logic state and a second capacitance when the digital input is in a second logic state; and adjusting a capacitance with respect to a second circuit node within the integrated circuit by applying the output to the second circuit node.

What is claimed is:  
     
         1 . An integrated circuit device comprising: 
 a first digital input;    a first parasitic capacitance block, the first parasitic capacitance block including an inverter, a variable capacitance element, and a wire capacitance element, the parasitic capacitance block having a capacitance that is a function of the first digital input;    a first output, the first output responsive to the first parasitic capacitance block;    a second digital input;    a second parasitic capacitance block; and    a second output, the second output responsive to the second parasitic capacitance block.    
     
     
         2 . The integrated circuit device of  claim 1 , wherein the second parasitic capacitance block includes a second inverter, a second variable capacitance element, and a second wire capacitance element, the second parasitic capacitance block having a capacitance that is a function of the second digital input.  
     
     
         3 . The integrated circuit device of  claim 1 , wherein the variable capacitance element further includes an intermediate circuit node.  
     
     
         4 . The integrated circuit device of  claim 1 , wherein the variable capacitance element has a first capacitance when the first digital input is in a first logic state and the variable capacitance has a second capacitance when the first digital input is in a second logic state.  
     
     
         5 . The integrated circuit device of  claim 1 , wherein the wire capacitance element has a substantially constant capacitance.  
     
     
         6 . The integrated circuit device of  claim 1 , wherein the variable capacitance element is in series with the wire capacitance element.  
     
     
         7 . The integrated circuit device of  claim 1 , wherein the wire capacitance element is connected to the first output.  
     
     
         8 . The integrated circuit device of  claim 1 , wherein the inverter is a weak inverter.  
     
     
         9 . The integrated circuit device of  claim 1 , wherein the weak inverter is constructed such that the weak inverter includes a transistor having a width that is substantially smaller than its length.  
     
     
         10 . The integrated circuit device of  claim 9 , wherein the width of the transistor is less than two times its length.  
     
     
         11 . An integrated circuit comprising: 
 a digital inverter;    a circuit node responsive to the digital inverter;    a first transistor having a first terminal coupled to the circuit node and a second terminal coupled to a voltage source;    a second transistor having a first terminal coupled to the circuit node and a second terminal coupled to ground;    a capacitor element responsive to the circuit node; and    an output coupled to the capacitor element.    
     
     
         12 . The integrated circuit of  claim 11 , wherein the digital inverter has a first terminal connected to a digital input, a second terminal connected to the voltage source, and a third terminal connected to ground.  
     
     
         13 . The integrated circuit of  claim 11 , wherein the inverter is a weak inverter and wherein the weak inverter is constructed such that the weak inverter has a transistor with a width that is substantially less than the transistor's length.  
     
     
         14 . The integrated circuit of  claim 11 , wherein the first transistor is a PMOS type of transistor and wherein the first terminal is a gate terminal of the PMOS transistor.  
     
     
         15 . The integrated circuit of  claim 14 , wherein the first transistor has a drain and a source terminal, the drain and the source terminal connected to the voltage source.  
     
     
         16 . The integrated circuit of  claim 11 , wherein the second transistor is an NMOS type of transistor and wherein the first terminal of the second transistor is a gate terminal.  
     
     
         17 . The integrated circuit of  claim 16 , wherein the second transistor has a drain and a source terminal, and wherein the drain and the source terminal of the second transistor are connected to ground.  
     
     
         18 . The integrated circuit of  claim 11 , wherein the capacitor element is a wire capacitor having an input terminal coupled to the circuit node and having an output terminal coupled to the output.  
     
     
         19 . The integrated circuit of  claim 11 , wherein when a first digital input value is applied to the digital inverter, the output is terminated to ground, the first transistor is in a deactive state, the second transistor is in an active state, and the circuit node is coupled to the voltage source.  
     
     
         20 . The integrated circuit of  claim 11 , wherein when a second digital input value is applied to the digital inverter, the output is terminated to the voltage source, the first transistor is in an active state, the second transistor is in a deactive state, and the circuit node is coupled to ground.  
     
     
         21 . An integrated circuit comprising: 
 a digital inverter;    an intermediate circuit node responsive to the digital inverter;    a transistor having a first terminal coupled to the intermediate circuit node and a second terminal coupled to ground;    a capacitor element responsive to the intermediate node; and    an output coupled to the capacitor element.    
     
     
         22 . The integrated circuit of  claim 21 , wherein the digital inverter has a first terminal connected to a digital input, a second terminal connected to the voltage source, and a third terminal connected to ground.  
     
     
         23 . The integrated circuit of  claim 21 , wherein the inverter is a weak inverter and wherein the weak inverter is constructed such that the weak inverter has a transistor with a width that is substantially less than the transistor's length.  
     
     
         24 . The integrated circuit of  claim 21 , wherein the transistor is an NMOS type of transistor and wherein the first terminal of the transistor is a gate terminal.  
     
     
         25 . The integrated circuit of  claim 24 , wherein the transistor has a drain and a source terminal, and wherein the drain and the source terminal of the transistor are connected to ground.  
     
     
         26 . The integrated circuit of  claim 21 , wherein the capacitor element is a wire capacitor having an input terminal coupled to the intermediate node and having an output terminal coupled to the output.  
     
     
         27 . The integrated circuit of  claim 21 , wherein when a first digital input value is applied to the digital inverter, the output is terminated to ground, the transistor is in an on state, and the intermediate node is coupled to the voltage source.  
     
     
         28 . The integrated circuit of  claim 21 , wherein when a second digital input value is applied to the digital inverter, the transistor is in an off state and the intermediate node is coupled to ground.  
     
     
         29 . The integrated circuit of  claim 21 , wherein when a second digital input value is applied to the digital inverter, the output is in a floating state.  
     
     
         30 . An integrated circuit comprising: 
 a digital inverter;    an intermediate circuit node responsive to an output terminal of the digital inverter;    a transistor having a first terminal coupled to the intermediate circuit node and a second terminal coupled to a voltage source;    a capacitor element responsive to the intermediate node; and    an output coupled to the capacitor element.    
     
     
         31 . The integrated circuit of  claim 30 , wherein the digital inverter has a first terminal coupled to a digital input, a second terminal coupled to the voltage source, and a third terminal is coupled to ground.  
     
     
         32 . The integrated circuit of  claim 30 , wherein the inverter is a weak inverter and wherein the weak inverter is constructed such that the weak inverter has a transistor with a width that is substantially less than the transistor's length.  
     
     
         33 . The integrated circuit of  claim 30 , wherein the transistor is a PMOS type of transistor and wherein the first terminal of the transistor is a gate terminal.  
     
     
         34 . The integrated circuit of  claim 30 , wherein the transistor has a drain and a source terminal, and wherein the drain and the source terminal of the transistor are coupled to the voltage source.  
     
     
         35 . The integrated circuit of  claim 30 , wherein the capacitor element is a wire capacitor having an input terminal coupled to the intermediate node and having a wire capacitor output terminal coupled to the output.  
     
     
         36 . The integrated circuit of  claim 30 , wherein when a first digital input value is applied to the digital inverter, the transistor is in an off state, and the intermediate node is coupled to the voltage source.  
     
     
         37 . The integrated circuit of  claim 30 , wherein when a second digital input value is applied to the digital inverter, the output is terminated to the voltage source, the transistor is in an on state and the intermediate node is coupled to ground.  
     
     
         38 . The integrated circuit of  claim 30 , wherein when a first digital input value is applied to the digital inverter, the output is in a floating state.  
     
     
         39 . An integrated circuit comprising: 
 a digital input;    a parasitic capacitance block, the parasitic capacitance block containing a first intermediate node, the parasitic capacitance block providing an output having a selectable capacitance, the output having a first capacitance when the digital input is in a first logic state and a second capacitance when the digital input is in a second logic state; and    circuit logic, the circuit logic containing a second intermediate node.    
     
     
         40 . The integrated circuit of  claim 39 , further comprising routing connection, the routing connection is responsive to the output of the parasitic capacitance block, the routing connection applying the output of the parasitic capacitance block to the second intermediate node to adjust capacitance of the second intermediate node.  
     
     
         41 . The integrated circuit of  claim 40 , wherein the routing connection is used to selectively modify capacitance of the second intermediate node by applying a first capacitance level when the digital input is in a first logic state and by applying a second capacitance level when the digital input is in a second logic state.  
     
     
         42 . The integrated circuit of  claim 39 , further comprising a plurality of parasitic capacitance blocks, each of the plurality of parasitic capacitance blocks having an output and each output having a different capacitance level.  
     
     
         43 . A method of adjusting a capacitor level for a node of an integrated circuit, the method comprising: 
 selecting a logic state of a digital input;    applying the digital input to a parasitic capacitance block having an output, the output having a first capacitance when the digital input is in first logic state and a second capacitance when the digital input is in a second logic state;    adjusting a capacitance with respect to a second circuit node within the integrated circuit by applying the output to the second circuit node.    
     
     
         44 . The method of  claim 43 , wherein the second circuit node is carrying an electronic signal having a frequency greater than one gigahertz.  
     
     
         45 . The method of  claim 43 , wherein the parasitic capacitance block contains a variable capacitance element in series with a wire capacitance element and wherein the variable capacitance element includes at least one active element having a first parasitic capacitance when the digital input is in a first logic state and having a second parasitic capacitance when the digital input is in a second logic state.  
     
     
         46 . The method of  claim 45 , wherein the active element comprises a transistor and wherein the parasitic capacitance includes a transistor gate capacitance.