Split gate flash memory cell structure and method of manufacturing the same

Abstract

A non-volatile memory cell that includes a semiconductor substrate, a well region implanted with a first-type dopant formed in the semiconductor substrate, a first doped region implanted with a second-type dopant formed in the semiconductor substrate, a second doped region, formed spaced-apart from the first doped region, implanted with a second-type dopant formed in the semiconductor substrate, the second doped region further including a third region implanted with the first-type dopant, a first dielectric layer disposed over the semiconductor substrate, a floating gate disposed over the first dielectric layer and extending over the well region and a portion of the second doped region, a second dielectric layer disposed over the floating gate, and a control gate disposed over the first dielectric layer and the second dielectric layer.

What is claimed is:  
     
         1 . A non-volatile memory cell, comprising: 
 a semiconductor substrate;    a well region implanted with a first-type dopant formed in the semiconductor substrate;    a first doped region implanted with a second-type dopant formed in the semiconductor substrate;    a second doped region, formed spaced-apart from the first doped region, implanted with a second-type dopant formed in the semiconductor substrate, the second doped region further including a third region implanted with the first-type dopant;    a first dielectric layer disposed over the semiconductor substrate;    a floating gate disposed over the first dielectric layer and extending over the well region and a portion of the second doped region;    a second dielectric layer disposed over the floating gate; and    a control gate disposed over the first dielectric layer and the second dielectric layer.    
     
     
         2 . The memory cell as claimed in  claim 1 , wherein the second doped region is a drain region and the first doped region is a source region.  
     
     
         3 . The memory cell as claimed in  claim 1 , wherein the second doped region is coupled to a bit line.  
     
     
         4 . The memory cell as claimed in  claim 1 , wherein the second doped region forms a parasitic transistor with the well region.  
     
     
         5 . The memory cell as claimed in  claim 4 , wherein the parasitic transistor conducts when a potential of the floating gate reaches a predetermined level.  
     
     
         6 . The memory cell as claimed in  claim 4 , wherein the parasitic transistor amplifies output signals of the memory cell.  
     
     
         7 . The memory cell as claimed in  claim 1 , wherein the second doped region and the well region amplifies an output signal of the memory cell.  
     
     
         8 . The memory cell as claimed in  claim 4 , wherein the parasitic transistor is a bipolar PNP transistor.  
     
     
         9 . The memory cell as claimed in  claim 1  further comprising a metal contact formed over the second doped region, wherein the metal contact is electrically coupled to the third region and isolated from the second doped region.  
     
     
         10 . A non-volatile memory product formed on a semiconductor substrate, comprising: 
 a memory cell including, 
 a well region doped with a first-type dopant,  
 a drain region having a first region doped with a first-type dopant and a second region doped with a second-type dopant, wherein the second region is contiguous with the well region,  
 a source region formed spaced-apart from the drain region and contiguous with the well region,  
 a floating gate disposed over the well region, drain region and source region, and  
 a control gate formed over the floating gate; and  
   a parasitic transistor formed inside the memory cell, wherein the memory cell attains a self-convergent state during programming of the memory cell.    
     
     
         11 . The non-volatile memory product as claimed in  claim 10 , wherein the parasitic transistor amplifies an output from the memory cell.  
     
     
         12 . The non-volatile memory product as claimed in  claim 10 , wherein the drain region of the memory cell is provided with a plurality of voltage levels to obtain a plurality of threshold voltages in the memory cell.  
     
     
         13 . The non-volatile memory product as claimed in  claim 12 , wherein the plurality of threshold voltages obtain a plurality of self-convergent states in the memory cell during programming.  
     
     
         14 . The non-volatile memory product as claimed in  claim 10 , wherein the source region and the well region are grounded during programming.  
     
     
         15 . The non-volatile memory product as claimed in  claim 10 , wherein the control gate is coupled to a voltage source for providing a step function during programming.  
     
     
         16 . A non-volatile memory product, comprising: 
 a semiconductor substrate, including 
 a well region implanted with a first-type dopant,  
 a first doped region implanted with a second-type dopant, and  
 a second doped region, formed spaced-apart from the first doped region, implanted with a second-type dopant, the second doped region including a third region implanted with the first-type dopant, wherein the second doped region and the well region form a parasitic transistor;  
   a floating gate disposed over the semiconductor substrate and a portion of the second doped region;    a control gate disposed over a portion of the floating gate;    a first voltage source for providing a first voltage to the second doped region; and    a second voltage source for providing a second voltage to the control gate,    wherein during programming of the memory cell, the first voltage is greater than the second voltage, and wherein upon reaching a predetermined programming level, the parasitic transistor conducts terminate programming.    
     
     
         17 . The non-volatile memory product as claimed in  claim 16 , wherein the parasitic transistor conducts to discharge the first voltage to a level substantially equal to that of the second voltage to terminate programming.  
     
     
         18 . The memory cell as claimed in  claim 16 , wherein the first voltage is a bit line voltage and the second voltage is a word line voltage.  
     
     
         19 . A method of self-convergent in programming of a non-volatile memory cell, comprising: 
 providing a non-volatile memory cell including a semiconductor substrate having a well region;    providing a parasitic transistor in the semiconductor substrate;    providing a first voltage sufficient to induce programming of the memory cell;    providing a floating gate over the semiconductor substrate;    providing a control gate over the semiconductor substrate and the floating gate;    providing a second voltage to the control gate, wherein the first voltage is larger than the second voltage; and    providing a predetermined programming parameter in the floating gate, wherein upon reaching the predetermined programming parameter, the parasitic transistor terminates programming.    
     
     
         20 . The method as claimed in  claim 19 , wherein the step of providing a parasitic transistor in the semiconductor substrate comprises 
 providing a first doped region in the semiconductor substrate,    providing a second doped region in the first doped region having a first-type dopant, and    providing a third doped region in the first doped region having a second-type dopant, wherein the first doped region and the well region forming a parasitic transistor.    
     
     
         21 . The method as claimed in  claim 19 , wherein the first voltage is a bit line voltage and the second voltage is a word line voltage.  
     
     
         22 . The method as claimed in  claim 19 , wherein the parasitic transistor conducts to discharge the first voltage to a level substantially equal to that of the second voltage.  
     
     
         23 . A method of multiple self-convergent states during programming of a non-volatile memory cell, comprising: 
 providing a non-volatile memory cell including a semiconductor substrate having a well region;    providing a parasitic transistor in the semiconductor substrate;    providing a first voltage sufficient to induce programming of the memory cell;    providing a floating gate over the semiconductor substrate;    providing a control gate over the semiconductor substrate and the floating gate;    providing a second voltage to the control gate, wherein the first voltage is larger than the second voltage,    providing a predetermined programming parameter in the floating gate, wherein upon reaching the predetermined programming parameter, the parasitic transistor conducts to terminate programming.    
     
     
         24 . The method as claimed in  claim 23 , wherein the step of providing a parasitic transistor in the semiconductor substrate comprises 
 providing a first doped region in the semiconductor substrate,    providing a second region in the first doped region having a first-type dopant, and    providing a third region in the first doped region having a second-type dopant, wherein the first doped region and the well region forming a parasitic transistor.    
     
     
         25 . The method as claimed in  claim 23 , wherein the step of providing a first voltage is to provide a first voltage to the first doped region.  
     
     
         26 . A method of forming a non-volatile memory cell, comprising: 
 forming a semiconductor substrate;    forming a well-region with a first-type dopant within the semiconductor substrate;    forming a floating gate;    forming a first spaced-apart region with a second-type dopant;    forming a region within the first spaced-apart region with the first-type dopant;    forming a second spaced-apart region with a second-type dopant; and forming a control gate.    
     
     
         27 . The method as claimed in  claim 26 , wherein the first-type dopant is a p-type dopant and the second-type dopant is an n-type dopant.