Circuit and method for generating a timing signal, and signal transmission system performing for high-speed signal transmission and reception between LSIs

Abstract

A signal transmission system has a plurality of signal lines, a plurality of transmitting circuits, a plurality of receiving circuits, and a timing adjusting circuit. The transmitting circuits are provided for the signal lines. Each of the receiving circuits receives a signal from a corresponding one of the transmitting circuits via the signal lines. The timing adjusting circuit, which is provided at the same side as the transmitting circuits, adjusts signal latch timing for the receiving circuits to optimum timing in accordance with signal skew caused between the signal lines. Therefore, a large-capacity and error free transmission can be performed at high speed using a plurality of signal lines without being affected by skew on each of the signal lines.

What is claimed is:  
     
         1 . A signal transmission system comprising: 
 a plurality of signal lines;    a plurality of transmitting circuits provided for said signal lines;    a plurality of receiving circuits each receiving a signal from a corresponding one of said transmitting circuits via said signal lines; and    a timing adjusting circuit, provided at the same side as said transmitting circuits, adjusting signal latch timing for said receiving circuits to optimum timing in accordance with signal skew caused between said signal lines.    
     
     
         2 . The signal transmission system as claimed in  claim 1 , further comprising a skew information detecting and transmitting circuit, detecting at the same side as said receiving circuits the signal skew caused between said signal lines, and transmitting information of said detected skew to said timing adjusting circuit.  
     
     
         3 . The signal transmission system as claimed in  claim 2 , wherein said skew information detecting and transmitting circuit detects the signal skew caused between said signal lines by receiving at said receiving circuits skew detection signals output from said transmitting circuits, and feeds skew information detected from said skew detection signals back to said timing adjusting circuit.  
     
     
         4 . The signal transmission system as claimed in  claim 3 , wherein said timing adjusting circuit comprises a selecting circuit, based on said skew information, an optimum clock for each of said transmitting circuits from among a plurality of clocks generated in advance.  
     
     
         5 . The signal transmission system as claimed in  claim 3 , wherein said skew detection signals are output when power is turned on to said system or at a predetermined timing, and the timing adjustment is performed based on said skew detection signals.  
     
     
         6 . The signal transmission system as claimed in  claim 1 , wherein said timing adjusting circuit provides an effective variable delay to a clock that drives each of said transmitting circuits.  
     
     
         7 . The signal transmission system as claimed in  claim 6 , wherein said timing adjusting circuit comprises a phase interpolator generating, from a plurality of clocks having different delay amounts, a new clock having a phase intermediate therebetween.  
     
     
         8 . The signal transmission system as claimed in  claim 1 , wherein said timing adjusting circuit provides an effective variable delay to a clock that drives each of said transmitting circuits and also to data that said each transmitting circuit outputs.  
     
     
         9 . The signal transmission system as claimed in  claim 8 , wherein said timing adjusting circuit comprises a phase interpolator generating, from a plurality of clocks having different delay amounts, a new clock having a phase intermediate therebetween.  
     
     
         10 . The signal transmission system as claimed in  claim 1 , wherein said timing adjusting circuit comprises an output timing adjusting circuit making output timing adjustable for each of said transmitting circuits for data that is input to said each transmitting circuit in synchronism with a clock common to said transmitting circuits.  
     
     
         11 . The signal transmission system as claimed in  claim 10 , wherein said timing adjusting circuit further comprises a clock comparing and generating circuit comparing a phase of an internal reference clock for said transmitting circuits with a phase of said common clock, and generating, based on the result of the phase comparison, a clock that is used to drive said transmitting circuits.  
     
     
         12 . The signal transmission system as claimed in  claim 1 , further comprising a receiving circuit clock generating circuit defining signal latch timing common to said receiving circuits.  
     
     
         13 . The signal transmission system as claimed in  claim 12 , wherein said receiving circuit clock generating circuit comprises: 
 a clock transmitting circuit provided at the same side as said transmitting circuits;    a single clock signal line; and    a clock receiving circuit receiving a clock signal from said clock transmitting circuit via said clock signal line, and applying said clock signal as a common clock to said receiving circuits.    
     
     
         14 . A timing signal generating circuit comprising: a candidate timing signal generating circuit generating a plurality of candidate timing signals with different phases; and 
 a receive timing signal control circuit selecting a receive timing signal to be used to receive data, from among said plurality of candidate timing signals in accordance with a prescribed condition, and holding said selected receive timing signal.    
     
     
         15 . The timing signal generating circuit as claimed in  claim 14 , wherein said receive timing signal control circuit comprises: 
 a test timing signal comparing circuit comparing a test timing signal, predetermined for each of said candidate timing signals, with a reference timing signal; and    a receive timing signal selection/holding circuit selecting and holding said receive timing signal in accordance with an output of said test timing signal comparing circuit.    
     
     
         16 . The timing signal generating circuit as claimed in  claim 15 , wherein a plurality of said test timing signals are set for each of said candidate timing signals, and said test timing signal comparing circuit compares said plurality of test timing signals with said reference timing signal.  
     
     
         17 . The timing signal generating circuit as claimed in  claim 16 , wherein said test timing signal comparing circuit compares said plurality of test timing signals with said reference timing signal a plurality of times, and said receive timing signal selection/holding circuit selects and holds said receive timing signal in accordance with the results of the plurality of comparisons made by said test timing signal comparing circuit.  
     
     
         18 . The timing signal generating circuit as claimed in  claim 15 , wherein said reference timing signal is supplied in parallel with said received data.  
     
     
         19 . The timing signal generating circuit as claimed in  claim 15 , wherein said reference timing signal is supplied by being included in a stream of said received data.  
     
     
         20 . The timing signal generating circuit as claimed  claim 15 , wherein said receive timing signal control circuit further comprises a receive timing signal releasing circuit releasing said selected and held receive timing signal in accordance with the output of said test timing signal comparing circuit.  
     
     
         21 . The timing signal generating circuit as claimed in  claim 20 , wherein when said receive timing signal is released by said receive timing signal releasing circuit, said receive timing signal selection/holding circuit selects and holds a new receive timing signal in accordance with the output of said test timing signal comparing circuit.  
     
     
         22 . The timing signal generating circuit as claimed in  claim 20 , wherein said receive timing signal control circuit further comprises a receive timing signal release notification circuit notifying a circuit external to said timing signal generating circuit of the releasing of said receive timing signal when said receive timing signal releasing circuit has released said selected and held receive timing signal.  
     
     
         23 . The timing signal generating circuit as claimed in  claim 20 , wherein a comparison condition in said test timing signal comparing circuit causing said receive timing signal releasing circuit to release said selected and held receive timing signal is relaxed compared with a comparison condition in said test timing signal comparing circuit causing said receive timing signal selection/holding circuit to select and hold said receive timing signal.  
     
     
         24 . The timing signal generating circuit as claimed in  claim 14 , wherein said receive timing signal control circuit further comprises a receive timing signal control disabling circuit externally disabling the selection of said receive timing signal from among said plurality of candidate timing signals and the holding of said selected receive timing signal.  
     
     
         25 . The timing signal generating circuit as claimed in  claim 14 , wherein said receive timing signal control circuit further comprises a receive timing signal control re-executing circuit externally re-executing the selection of said receive timing signal from among said plurality of candidate timing signals and the holding of said selected receive timing signal.  
     
     
         26 . A signal transmission system comprising a transmitting circuit transmitting data, a signal transmission line, and a receiving circuit receiving data transmitted from said transmitting circuit over said signal transmission line, wherein said receiving circuit comprises a timing signal generating circuit comprising: 
 a candidate timing signal generating circuit generating a plurality of candidate timing signals with different phases; and    a receive timing signal control circuit selecting a receive timing signal to be used to receive data, from among said plurality of candidate timing signals in accordance with a prescribed condition, and holding said selected receive timing signal.    
     
     
         27 . The signal transmission system as claimed in  claim 26 , wherein said receive timing signal control circuit comprises: 
 a test timing signal comparing circuit comparing a test timing signal, predetermined for each of said candidate timing signals, with a reference timing signal; and    a receive timing signal selection/holding circuit selecting and holding said receive timing signal in accordance with an output of said test timing signal comparing circuit.    
     
     
         28 . The signal transmission system as claimed in  claim 27 , wherein a plurality of said test timing signals are set for each of said candidate timing signals, and said test timing signal comparing circuit compares said plurality of test timing signals with said reference timing signal.  
     
     
         29 . The signal transmission system as claimed in  claim 28 , wherein said test timing signal comparing circuit compares said plurality of test timing signals with said reference timing signal a plurality of times, and said receive timing signal selection/holding circuit selects and holds said receive timing signal in accordance with the results of the plurality of comparisons made by said test timing signal comparing circuit.  
     
     
         30 . The signal transmission system as claimed in  claim 27 , wherein said reference timing signal is supplied in parallel with said received data.  
     
     
         31 . The signal transmission system as claimed in  claim 27 , wherein said reference timing signal is supplied by being included in a stream of said received data.  
     
     
         32 . The signal transmission system as claimed in  claim 27 , wherein said receive timing signal control circuit further comprises a receive timing signal releasing circuit releasing said selected and held receive timing signal in accordance with the output of said test timing signal comparing circuit.  
     
     
         33 . The signal transmission system as claimed in  claim 32 , wherein when said receive timing signal is released by said receive timing signal releasing circuit, said receive timing signal selection/holding circuit selects and holds a new receive timing signal in accordance with the output of said test timing signal comparing circuit.  
     
     
         34 . The signal transmission system as claimed in  claim 32 , wherein said receive timing signal control circuit further comprises a receive timing signal release notification circuit notifying a circuit external to said timing signal generating circuit of the releasing of said receive timing signal when said receive timing signal releasing circuit has released said selected and held receive timing signal.  
     
     
         35 . The signal transmission system as claimed in  claim 32 , wherein a comparison condition in said test timing signal comparing circuit causing said receive timing signal releasing circuit to release said selected and held receive timing signal is relaxed compared with a comparison condition in said test timing signal comparing circuit causing said receive timing signal selection/holding circuit to select and hold said receive timing signal.  
     
     
         36 . The signal transmission system as claimed in  claim 26 , wherein said receive timing signal control circuit further comprises a receive timing signal control disabling circuit externally disabling the selection of said receive timing signal from among said plurality of candidate timing signals and the holding of said selected receive timing signal.  
     
     
         37 . The signal transmission system as claimed in  claim 26 , wherein said receive timing signal control circuit further comprises a receive timing signal control re-executing circuit externally re-executing the selection of said receive timing signal from among said plurality of candidate timing signals and the holding of said selected receive timing signal.  
     
     
         38 . A timing signal generating method comprising the steps of: 
 preparing a plurality of candidate timing signals with different phases; and    selecting a receive timing signal to be used to receive data, from among said plurality of candidate timing signals in accordance with a prescribed condition, and holding said selected receive timing signal.    
     
     
         39 . The timing signal generating method as claimed in  claim 38 , wherein the step of selecting and holding of said receive timing signal comprises the steps of: 
 comparing a test timing signal, predetermined for each of said candidate timing signals, with a reference timing signal; and    selecting and holding said receive timing signal in accordance with the result of the comparison between said test timing signal for said each candidate timing signal and said reference timing signal.    
     
     
         40 . The timing signal generating method as claimed in  claim 39 , wherein a plurality of said test timing signals are set for each of said candidate timing signals, and said plurality of test timing signals are compared with said reference timing signal.  
     
     
         41 . The timing signal generating method as claimed in  claim 40 , wherein said plurality of test timing signals are compared with said reference timing signal a plurality of times, and said receive timing signal are selected and held in accordance with the results of the plurality of comparisons made between said plurality of test timing signals and said reference timing signal.  
     
     
         42 . The timing signal generating method as claimed in  claim 39 , wherein said reference timing signal is supplied in parallel with said received data.  
     
     
         43 . The timing signal generating method as claimed in  claim 39 , wherein said reference timing signal is supplied by being included in a stream of said received data.  
     
     
         44 . The timing signal generating method as claimed in  claim 39 , wherein the selection and holding of said receive timing signal further includes releasing said selected and held receive timing signal in accordance with the result of the comparison between said test timing signal for said each candidate timing signal and said reference timing signal.  
     
     
         45 . The timing signal generating method as claimed in  claim 44 , wherein when said receive timing signal is released, said test timing signal predetermined for each of said candidate timing signals is compared with said reference timing signal to select and hold a new receive timing signal.  
     
     
         46 . The timing signal generating method as claimed in  claim 44 , wherein when said selected and held receive timing signal is released, the releasing of said receive timing signal is notified to an external circuit.  
     
     
         47 . The timing signal generating method as claimed in  claim 44 , wherein a comparison condition for releasing said selected and held receive timing signal is relaxed compared with a comparison condition for selecting and holding said receive timing signal.  
     
     
         48 . The timing signal generating method as claimed in  claim 38 , wherein the selection of said receive timing signal from among said plurality of candidate timing signals and the holding of said selected receive timing signal are disabled from outside.  
     
     
         49 . The timing signal generating method as claimed in  claim 38 , the selection of said receive timing signal from among said plurality of candidate timing signals and the holding of said selected receive timing signal are re-executed from outside.