Recording and reproducing apparatus, signal decoding circuit, error correction method and iterative decoder

Abstract

A recording and reproducing apparatus having an error correction function ECC-less, includes a erasure detector generating an erasure flag indicating disappearance of a read signal; and an iterative decoder having two soft-in/soft-out (SISO) decoders, i.e., an inner decoder and an outer decoder, and correcting the erasure by inputting the erasure flag e k into the inner decoder 84 and performing erasure compensation in the inner decoder. As the erasure compensation in the inner decoder, channel information is masked while the erasure flag is on. The erasure of data due to a media defect is detected inside the iterative decoder, and the second erasure flag is inputted into the inner decoder to perform erasure compensation in the inner decoder.

What is claimed is:  
     
         1 . A recording and reproducing apparatus comprising: 
 an erasure detector generating an erasure flag indicating disappearance of a read signal; and    an iterative decoder having two soft-in/soft-out decoders, the two soft-in/soft-out decoders being an inner decoder and an outer decoder, the iterative decoder correcting the erasure of the read signal by inputting said erasure flag into the inner decoder and performing erasure compensation in the inner decoder.    
     
     
         2 . The apparatus according to  claim 1 , wherein 
 as the erasure compensation in said inner decoder, channel information is masked while said erasure flag is on.    
     
     
         3 . The apparatus according to  claim 1 , wherein 
 said erasure detector detects thermal asperity and generates the erasure flag indicating the disappearance of the read signal.    
     
     
         4 . The apparatus according to  claim 1 , wherein 
 said inner decoder is the soft-in/soft-out decoder based on a BCJR (Bahl-Cocke-Jeinek-Raviv) decoding method; and if said erasure flag is on, channel information is masked with 0 in the inner decoder.    
     
     
         5 . The apparatus according to  claim 1 , wherein 
 said inner decoder is the soft-in/soft-out decoder based on a BCJR (Bahl-Cocke-Jeinek-Raviv) decoding method; and if said erasure flag is on, an exponential value of channel information is masked with 1 in the inner decoder.    
     
     
         6 . The apparatus according to  claim 1 , wherein 
 said inner decoder is the soft-in/soft-out decoder based on a logarithm maximum a posteriori probability (LogMAP) decodingmethod; and if said erasure flag is on, channel information is masked with 0 in the inner decoder.    
     
     
         7 . The apparatus according to  claim 1 , wherein 
 said inner decoder is the soft-in/soft-out decoder based on an approximation type logarithm maximum a posteriori probability (MaxLogMAP) decoding method; and if said erasure flag is on, channel information is masked with 0 in the inner decoder.    
     
     
         8 . The apparatus according to  claim 1 , wherein 
 said inner decoder is the soft-in/soft-out decoder based on a soft output Viterbi algorithm (SOVA) decoding method; and if said erasure flag is on, channel information is masked with 0 in the inner decoder.    
     
     
         9 . The apparatus according to  claim 1 , wherein 
 said erasure detector expands forward a leading edge of the erasure flag by a predetermined number of bits.    
     
     
         10 . The apparatus according to  claim 1 , wherein 
 said disappearance detector expands backward a trailing edge of the erasure flag by a predetermined number of bits.    
     
     
         11 . The apparatus according to  claim 1 , wherein 
 a second erasure detector generating a second erasure flag indicating the disappearance of the read signal is provided in said iterative decoder; and a logical sum of the first erasure flag and the second erasure flag by said second erasure detector is inputted into the inner decoder.    
     
     
         12 . The apparatus according to  claim 11 , wherein 
 said second erasure detector generates the second erasure flag by checking violation of an RLL constraint.    
     
     
         13 . The apparatus according to  claim 12 , wherein 
 said second disappearance detector generates the second erasure flag only if a number of times of the violation of the RLL constraint is equal to or higher than a predetermined number.    
     
     
         14 . A signal decoding circuit comprising: 
 an erasure detector generating an erasure flag indicating disappearance of a read signal; and    an iterative decoder having two soft-in/soft-out decoders, the two soft-in/soft-out decoders being an inner decoder and an outer decoder, the iterative decoder correcting the disappearance of the read signal by inputting said erasure flag into the inner decoder and performing erasure compensation in the inner decoder.    
     
     
         15 . The signal decoding circuit according to  claim 14 , wherein 
 as the erasure compensation in said inner decoder, channel information is masked while said erasure flag is on.    
     
     
         16 . The signal decoding circuit according to  claim 14 , wherein 
 said disappearance detector detects thermal asperity and generates the erasure flag indicating the disappearance of the read signal.    
     
     
         17 . The signal decoding circuit according to  claim 14 , wherein 
 said inner decoder is the soft-in/soft-out decoder based on a BCJR (Bahl-Cocke-Jeinek-Raviv) decoding method; and if said erasure flag is on, channel information is masked with 0 in the inner decoder.    
     
     
         18 . The signal decoding circuit according to  claim 14 , wherein 
 said inner decoder is the soft-in/soft-out decoder based on a BCJR (Bahl-Cocke-Jeinek-Raviv) decoding method; and if said erasure flag is on, an exponential value of channel information is masked with 1 in the inner decoder.    
     
     
         19 . The signal decoding circuit according to  claim 14 , wherein 
 said inner decoder is the soft-in/soft-out decoder based on a logarithm maximum a posteriori probability (LogMAP) decoding method; and if said erasure flag is on, channel information is masked with 0 in the inner decoder.    
     
     
         20 . The signal decoding circuit according to  claim 14 , wherein 
 said inner decoder is the soft-in/soft-out decoder based on an approximation type logarithm maximum a posteriori probability (MaxLogMAP) decoding method; and if said erasure flag is on, channel information is masked with 0 in the inner decoder.    
     
     
         21 . The signal decoding circuit according to  claim 14 , wherein 
 said inner decoder is the soft-in/soft-out decoder based on a soft output Viterbi algorithm (SOVA) decoding method; and if said erasure flag is on, channel information is masked with 0 in the inner decoder.    
     
     
         22 . The signal decoding circuit according to  claim 14 , wherein 
 said erasure detector expands forward a leading edge of the erasure flag by a predetermined number of bits.    
     
     
         23 . The signal decoding circuit according to  claim 14 , wherein 
 said erasure detector expands backward a trailing edge of the erasure flag by a predetermined number of bits.    
     
     
         24 . The signal decoding circuit according to  claim 14 , wherein 
 a second erasure detector generating a second erasure flag indicating the disappearance of the read signal is provided in said iterative decoder; and a logical sum of the first erasure flag and the second erasure flag by said second erasure detector is inputted into the inner decoder.    
     
     
         25 . The signal decoding circuit according to  claim 24 , wherein 
 said second erasure detector generates the second erasure flag by checking violation of an RLL constraint.    
     
     
         26 . The signal decoding circuit according to  claim 25 , wherein 
 said second erasure detector generates the second erasure flag only if a number of times of the violation of the RLL constraint is equal to or higher than a predetermined number.    
     
     
         27 . An error correction method for decoding a read signal by an iterative decoder comprising two soft-in/soft-out decoders, the two soft-in/soft-out decoders being an inner decoder and an outer decoder, the method comprising the steps of: 
 generating an erasure flag indicating disappearance of said read data; and    inputting said erasure flag into said inner decoder, performing erasure compensation in the inner decoder, and thereby correcting the disappearance.    
     
     
         28 . The method according to  claim 27 , wherein 
 a second erasure detector detecting a second erasure flag indicating the disappearance of the read signal is provided in said iterative decoder; and a logical sum of the first erasure flag and the second erasure flag by said second erasure detector is inputted into the inner decoder.    
     
     
         29 . An iterative decoder comprising two soft-in/soft-out decoders, the two soft-in/soft-out decoders being an inner decoder and an outer decoder, inputting an external erasure flag indicating disappearance of a read signal into the inner decoder, performing erasure compensation in the inner decoder, and thereby correcting lost data.  
     
     
         30 . The iterative decoder according to  claim 29 , wherein 
 an erasure detector generating an internal erasure flag indicating the disappearance of the read signal is provided in said iterative decoder; and a logical sum of said external erasure flag and said inner erasure flag is inputted into the inner decoder.