High speed input

Abstract

A high speed input buffer of the type having a first connection in electrical communication with a positive voltage source and a second connection in electrical communication with a negative voltage source. A first native transistor is functionally disposed between the positive voltage source and the first connection. A first contact of the first native transistor is electrically connected to the positive voltage source and a second contact of the first native transistor is electrically connected to the first connection. A second native transistor is functionally disposed between the negative voltage source and the second connection. A first contact of the second native transistor is electrically connected to the negative voltage source and a second contact of the second native transistor is electrically connected to the second connection.

What is claimed is:  
     
         1 . In a high speed input buffer of the type having a first connection in electrical communication with a positive voltage source and a second connection in electrical communication with a negative voltage source, the improvement comprising a first native transistor functionally disposed between the positive voltage source and the first connection, with a first contact of the first native transistor electrically connected to the positive voltage source and a second contact of the first native transistor electrically connected to the first connection, and a second native transistor functionally disposed between the negative voltage source and the second connection, with a first contact of the second native transistor electrically connected to the negative voltage source and a second contact of the second native transistor electrically connected to the second connection.  
     
     
         2 . The high speed input buffer of  claim 1  wherein the first native transistor comprises a native NMOS transistor.  
     
     
         3 . The high speed input buffer of  claim 1  wherein the second native transistor comprises a native NMOS transistor.  
     
     
         4 . The high speed input buffer of  claim 1  further comprising a leakage element having a first electrical connection and a second electrical connection, the first electrical connection of the leakage element electrically connected to the second contact of the first native transistor and the second electrical connection of the leakage element electrically connected to a VSS line.  
     
     
         5 . The high speed input buffer of  claim 4  wherein the leakage element comprises an NMOS transistor, where a gate contact of the NMOS transistor is also electrically connected to the second contact of the first native transistor.  
     
     
         6 . The high speed input buffer of  claim 4  wherein the leakage element comprises a resistor.  
     
     
         7 . The high speed input buffer of  claim 4  wherein the leakage element has a leakage current of about one microampere.  
     
     
         8 . The high speed input buffer of  claim 1  further comprising a leakage element having a first electrical connection and a second electrical connection, the first electrical connection of the leakage element electrically connected to the second contact of the second native transistor and the second electrical connection of the leakage element electrically connected to a VSS line.  
     
     
         9 . The high speed input buffer of  claim 8  wherein the leakage element comprises an NMOS transistor, where a gate contact of the NMOS transistor is also electrically connected to the second contact of the second native transistor.  
     
     
         10 . The high speed input buffer of  claim 8  wherein the leakage element comprises a resistor.  
     
     
         11 . The high speed input buffer of  claim 8  wherein the leakage element has a leakage current of about one microampere.  
     
     
         12 . The high speed input buffer of  claim 1  wherein the first native transistor has a drain dopant profile that tolerates a drain voltage that is greater than a gate voltage for which the first native transistor is designed to tolerate.  
     
     
         13 . The high speed input buffer of  claim 12  wherein the drain voltage is about five volts and the gate voltage is about 3.3 volts.  
     
     
         14 . The high speed input buffer of  claim 1  wherein the second native transistor has a drain dopant profile that tolerates a drain voltage that is greater than a gate voltage for which the second native transistor is designed to tolerate.  
     
     
         15 . The high speed input buffer of  claim 14  wherein the drain voltage is about five volts and the gate voltage is about 3.3 volts.  
     
     
         16 . An integrated circuit including the high speed input buffer of  claim 1 .  
     
     
         17 . A buffered high speed input electrically connected to an input voltage pad, the buffered high speed input comprising: 
 a native transistor having a first contact electrically connected to the input voltage pad, and    a single ended input electrically connected to a second contact of the native transistor.    
     
     
         18 . The buffered high speed input of  claim 17  wherein the native transistor comprises a native NMOS transistor.  
     
     
         19 . The buffered high speed input of  claim 17  further comprising a leakage element having a first electrical connection and a second electrical connection, the first electrical connection of the leakage element electrically connected to the second contact of the first native transistor and the second electrical connection of the leakage element electrically connected to a VSS line.  
     
     
         20 . An integrated circuit, the improvement comprising the buffered high speed input of  claim 17.